AT49BV001A-55VI Atmel, AT49BV001A-55VI Datasheet - Page 3

• Manufacturer Part Number: AT49BV001A-55VI
• Description: IC FLASH 1MBIT 55NS 32VSOP
• Manufacturer: Atmel

Specifications of AT49BV001A-55VI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3. Block Diagram
4. Device Operation
4.1
4.2
4.3
3364D–FLASH–3/05
Read
Command Sequences
Reset
The AT49BV001A(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins is asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
When the device is first powered on it will be reset to the read or standby mode depending upon
the state of the control line inputs. In order to perform other device functions, a series of com-
mand sequences are entered into the device. The command sequences are shown in the
“Command Definition Table” on page
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is
latched on the falling edge of CE or WE (except for the sixth cycle of the Sector Erase com-
mand), whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences
are not affected by entering the command sequences.
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program or erase operation, the operation
may not be successfully completed and the operation will have to be repeated after a high level
is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device
returns to the read or standby mode, depending upon the state of the control inputs. By applying
a 12V ± 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if
the boot block lockout feature has been enabled (see
page
4). The RESET feature is not available on the AT49BV001AN(T).
ADDRESS
INPUTS
RESET
GND
VCC
WE
OE
CE
Y DECODER
X DECODER
CONTROL
LOGIC
6. The command sequences are written by applying a low
DATA INPUTS/OUTPUTS
DATA LATCHES
AT49BV001A(N)
INPUT/OUTPUT
MAIN MEMORY
MAIN MEMORY
BOOT BLOCK
PARAMETER
PARAMETER
(64K BYTES)
(32K BYTES)
(16K BYTES)
(8K BYTES)
(8K BYTES)
PROGRAM
I/O7 - I/O0
Y-GATING
BUFFERS
BLOCK 2
BLOCK 1
BLOCK 2
BLOCK 1
8
“Boot Block Programming Lockout” on
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
AT49BV001A(N)(T)
DATA INPUTS/OUTPUTS
AT49BV001A(N)T
DATA LATCHES
INPUT/OUTPUT
MAIN MEMORY
MAIN MEMORY
BOOT BLOCK
PARAMETER
(16K BYTES)
PARAMETER
(32K BYTES)
(64K BYTES)
(8K BYTES)
(8K BYTES)
PROGRAM
I/O7 - I/O0
BUFFERS
Y-GATING
BLOCK 1
BLOCK 2
BLOCK 1
BLOCK 2
8
1FFFF
1C000
1BFFF
1A000
19FFF
18000
17FFF
10000
0FFFF
00000
3