AT45DB041B-TI-2.5 Atmel, AT45DB041B-TI-2.5 Datasheet - Page 7
![IC FLASH 4MBIT 20MHZ 28TSOP](/photos/7/21/72191/313-28-tsop_sml.jpg)
AT45DB041B-TI-2.5
Manufacturer Part Number
AT45DB041B-TI-2.5
Description
IC FLASH 4MBIT 20MHZ 28TSOP
Manufacturer
Atmel
Datasheet
1.AT45DB041B-CC.pdf
(35 pages)
Specifications of AT45DB041B-TI-2.5
Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
4M (2048 pages x 264 bytes)
Speed
20MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
5.2.4
5.2.5
Table 5-2.
3443D–DFLSH–2/08
PA10
0
0
0
0
1
1
1
1
•
•
•
Page Erase
Block Erase
PA9
Block Erase Addressing
0
0
0
0
1
1
1
1
•
•
•
PA8
0
0
0
0
1
1
1
1
•
•
•
Successive page programming operations without doing a page erase are not recommended. In
other words, changing bytes within a page from a “1” to a “0” during multiple page programming
operations without erasing that page is not recommended.
The optional Page Erase command can be used to individually erase any page in the main
memory array allowing the Buffer to Main Memory Page Program without Built-in Erase com-
mand to be utilized at a later time. To perform a Page Erase, an opcode of 81H must be loaded
into the device, followed by four reserved bits, 11 address bits (PA10 - PA0), and nine don’t care
bits. The 11 address bits are used to specify which page of the memory array is to be erased.
When a low-to-high transition occurs on the CS pin, the part will erase the selected page to 1s.
The erase operation is internally self-timed and should take place in a maximum time of t
ing this time, the status register will indicate that the part is busy.
A block of eight pages can be erased at one time allowing the Buffer to Main Memory Page Pro-
gram without Built-in Erase command to be utilized to reduce programming times when writing
large amounts of data to the device. To perform a Block Erase, an opcode of 50H must be
loaded into the device, followed by four reserved bits, eight address bits (PA10 - PA3), and 12
don’t care bits. The eight address bits are used to specify which block of eight pages is to be
erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected
block of eight pages to 1s. The erase operation is internally self-timed and should take place in a
maximum time of t
PA7
0
0
0
0
1
1
1
1
•
•
•
PA6
BE
0
0
0
0
1
1
1
1
•
•
•
. During this time, the status register will indicate that the part is busy.
PA5
0
0
0
0
1
1
1
1
•
•
•
PA4
0
0
1
1
0
0
1
1
•
•
•
PA3
0
1
0
1
0
1
0
1
•
•
•
PA2
X
X
X
X
X
X
X
X
•
•
•
PA1
X
X
X
X
X
X
X
X
•
•
•
AT45DB041B
PA0
X
X
X
X
X
X
X
X
•
•
•
Block
252
253
254
255
PE
0
1
2
3
•
•
•
. Dur-
7