AT25256W-10SI-2.7 Atmel, AT25256W-10SI-2.7 Datasheet - Page 7

• Manufacturer Part Number: AT25256W-10SI-2.7
• Description: IC EEPROM 256KBIT 3MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25256W-10SI-2.7

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 2.1MHz, 3MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

0872O–SEEPR–03/05
WRITE ENABLE (WREN): The device will power-up in the write disable state when V
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The Ready/Busy and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR instruc-
tion.
Table 6. Status Register Format
Table 7. Read Status Register Bit Definition
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25128/256 is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of
the data within any selected segment will therefore be READ only. The block write pro-
tection levels and corresponding status register control bits are shown in Table 8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, t
Table 8. Block Write Protect Bits
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4 - 6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
Bits 0 – 7 are “1”s during an internal write cycle.
1(1/4)
2(1/2)
WPEN
Level
3(All)
Bit 7
0
Bit 6
X
BP1
Status Register Bits
0
0
1
1
Definition
Bit 0 = “0” (RDY) indicates the device is READY.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 = “0” indicates the device is not WRITE ENABLED. Bit 1 = 1
indicates the device is WRITE ENABLED.
See Table 8.
See Table 8.
See Table 9.
Bit 5
X
BP0
0
1
0
1
Bit 4
X
Bit 3
BP1
3000 - 3FFF
2000 - 3FFF
0000 - 3FFF
AT25128
Array Addresses Protected
None
WC
Bit 2
BP0
, RDSR).
AT25128/256
WEN
Bit 1
6000 - 7FFF
4000 - 7FFF
0000 - 7FFF
AT25256
None
Bit 0
RDY
CC
7