AT49BV4096A-15RC Atmel, AT49BV4096A-15RC Datasheet - Page 3

• Manufacturer Part Number: AT49BV4096A-15RC
• Description: IC FLASH 4MBIT 150NS 44SOIC
• Manufacturer: Atmel

Specifications of AT49BV4096A-15RC

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8 or 256K x 16)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT49BV4096A15RC

Description
(Continued)
Block Diagram
Device Operation
1618F–FLASH–11/02
The device is erased by executing the Erase command sequence; the device internally
controls the erase operation. The memory is divided into four blocks for erase opera-
tions. There are two 4K word parameter block sections, the boot block, and the main
memory array block. The typical number of program and erase cycles is in excess of
10,000 cycles.
The 8K word boot block section includes a reprogramming lock out feature to provide
data integrity. This feature is enabled by a command sequence. Once the boot block
programming lockout feature is enabled, the data in the boot block cannot be changed
when input levels of 5.5 volts or less are used. The boot sector is designed to contain
user secure code.
The BYTE pin controls whether the device data I/O pins operate in the byte or word con-
figuration. If the BYTE pin is set at a logic “1” or left open, the device is in word
configuration, I/O0 - I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O
pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function.
READ: The AT49BV/LV4096A is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high-impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the
read or standby mode, depending upon the state of the control line inputs. In order to
perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the Command Definitions table (I/O8 -
I/O15 are don’t care inputs for the command codes). The command sequences are writ-
ten by applying a low pulse on the WE or CE input with CE or WE low (respectively) and
OE high. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Standard microprocessor write
ADDRESS
INPUTS
RESET
VCC
GND
WE
OE
CE
Y DECODER
X DECODER
CONTROL
LOGIC
DATA INPUTS/OUTPUTS
PROGRAM DATA
INPUT/OUTPUT
MAIN MEMORY
(240K WORDS)
AT49BV/LV4096A
PARAMETER
PARAMETER
BOOT BLOCK
I/O0 - I/O15
4K WORDS
4K WORDS
BUFFERS
LATCHES
Y-GATING
8K WORDS
BLOCK 2
BLOCK 1
3FFFF
03FFF
02FFF
01FFF
00000
04000
03000
02000
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