AT24C64N-10SI Atmel, AT24C64N-10SI Datasheet - Page 6
![IC EEPROM 64KBIT 400KHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
AT24C64N-10SI
Manufacturer Part Number
AT24C64N-10SI
Description
IC EEPROM 64KBIT 400KHZ 8SOIC
Manufacturer
Atmel
Datasheet
1.AT24C32-10PC.pdf
(19 pages)
Specifications of AT24C64N-10SI
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT24C64N-10SI-1.8
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT24C64N-10SI-2.5
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT24C64N-10SI-2.7
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT24C64N-10SI2.7
Manufacturer:
ATMEL
Quantity:
242
Part Number:
AT24C64N-10SI2.7
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32/64 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
AT24C32/64
6
0336K–SEEPR–7/03