24LCS61/SN Microchip Technology, 24LCS61/SN Datasheet - Page 8
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24LCS61/SN
Manufacturer Part Number
24LCS61/SN
Description
IC EEPROM 1KBIT 400KHZ 8SOIC
Manufacturer
Microchip Technology
Datasheet
1.24LCS61-IP.pdf
(22 pages)
Specifications of 24LCS61/SN
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
1K (128 x 8)
Speed
100kHz, 400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
24LCS61/24LCS62
5.2
The Clear Address command will clear the device ID
byte from all devices on the bus and will enable all
devices to respond to the Assign Address command.
The master must end the command by sending an ACK
after 8 don’t care bits have been transmitted, followed
by a Stop bit. Sending the Stop bit in any other position
of the command will result in the command aborting
and the device releasing the bus.
FIGURE 5-2:
5.3
The diagram below shows the state diagram for basic
operation of the 24LCS61/62. This diagram shows
possible states and operational flow once power is
applied to the device. Table 5-1 summarizes operation
of each command for the assigned and unassigned
states.
FIGURE 5-3:
DS21226E-page 8
Clear Address Command
Operation State Diagram
Power
Off
CLEAR ADDRESS COMMAND
OPERATIONAL STATE DIAGRAM
Power Off
Power On
S
T
A
R
T
S
0
1
CONTROL
1 0
BYTE
(ID byte not assigned yet)
Assign Address Command:
Device loses Arbitration
O
E
1 1
Unassigned
Power Off
State
0
A
C
K
X X X X X X X X
Device ID Byte
Clear Address
Command
A
C
K
Assign Address Command:
Device wins Arbitration
S
T
O
P
P
(ID byte has been assigned)
2004 Microchip Technology Inc.
Assigned
State