24LCS61-I/ST Microchip Technology, 24LCS61-I/ST Datasheet - Page 6
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24LCS61-I/ST
Manufacturer Part Number
24LCS61-I/ST
Description
IC EEPROM 1KBIT 400KHZ 8TSSOP
Manufacturer
Microchip Technology
Datasheet
1.24LCS61-IP.pdf
(22 pages)
Specifications of 24LCS61-I/ST
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
1K (128 x 8)
Speed
100kHz, 400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
24LCS61/24LCS62
4.0
The 24LCS61/62 supports a bidirectional 2-wire bus
and data transmission protocol compatible with the I
protocol. The device is configured to reside on a
common I
devices on the bus. Each device has a unique serial
number assigned to it when delivered from the factory.
In an actual system, this serial number will be used to
assign a separate 8-bit ID byte to each device in the
system. After an ID byte is assigned to each device in
the system, standard Read and Write commands can
be sent to each device individually.
4.1
The device serial number is stored in a 48-bit (6 byte)
register that is separate from the data array. The serial
number register is nonvolatile and cannot be changed
by the user. Before shipment from the factory, this
register is programmed with a unique value for every
device. The 48 bit register allows for 2.8 10
combinations. The serial number is used at power-up
to assign the device an ID byte which is then used for
all standard Read and Write commands sent to that
specific device.
4.2
The Device ID byte is an 8-bit value that provides the
means for every device on the bus to be accessed
individually. The ID byte is stored in a RAM register
separate from the data array. The ID byte register will
always default to address 00 upon power-up.
4.3
Each command to the device must begin with a Start
bit. A control byte is the first byte received following the
Start condition from the master device (Figure 4-1).
The control byte consists of a four-bit control code, the
OE bit, and three command select bits. For the
24LCS61/62, the control code is set to ‘0110’ binary for
all operations. The device will not acknowledge any
commands sent with any other control code. The next
bit is the Output Enable (OE) bit. This bit controls the
operation of the EDS pin. See Section 9.0 “External
Device Select (EDS) Pin and Output Enable (OE)
Bit” for more details. The last three bits of the control
byte are the command select bits (C0-C2). The
command select bits determine which command will be
executed. See Table 4-1. Following a valid control byte,
the 24LCS61/62 will acknowledge the command.
DS21226E-page 6
FUNCTIONAL DESCRIPTION
Device Serial Number
Device ID Byte
Device Addressing
2
C bus with up to 255 total 24LCS61/62
14
different
2
C
FIGURE 4-1:
TABLE 4-1:
Set Write Protection Fuse
Read
Write (Byte or Page)
Assign Address
Clear Address
Start Bit
S
Command
0
Output Enable
Control Code
1
Bit
COMMAND CODES
1
CONTROL BYTE FORMAT
2004 Microchip Technology Inc.
0
OE
Command Select Bits
Acknowledge Bit
Command Select
C2
(C2 C1 C0)
Bits
C1
000
001
010
100
110
C0
ACK