24LC164-I/SN Microchip Technology, 24LC164-I/SN Datasheet - Page 5

• Manufacturer Part Number: 24LC164-I/SN
• Description: IC EEPROM 16KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC164-I/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (2K x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

3.6
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one, a read operation is
selected. When set to ‘0’ a write operation is selected.
Following the start condition, the 24LC164 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC164 will select a read
or write operation.
FIGURE 3-2:
 2004 Microchip Technology Inc.
Operation
Read
Write
MSB
1
Device Addressing
START
A2
1
1
Control Code
SLAVE ADDRESS
A2 A1 A0 Block Address
A2 A1 A0 Block Address
A1
CONTROL BYTE
ALLOCATION
A0
B2
READ/WRITE
Block Select
B1
R/W
LSB
B0
A
R/W
1
0
4.0
4.1
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic LOW, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC164. After
receiving another acknowledge signal from the
24LC164, the master device will transmit the data word
to be written into the addressed memory location. The
24LC164 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle. During this time the 24LC164 will not generate
acknowledge signals (Figure 4-1).
4.2
The write control byte, word address and the first data
byte are transmitted to the 24LC164 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 16 data bytes to the
24LC164 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
Note:
WRITE OPERATION
Byte Write
Page Write
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
24LC164
DS21093I-page 5