UPD44646363AF5-E22-FQ1-A Renesas Electronics America, UPD44646363AF5-E22-FQ1-A Datasheet
UPD44646363AF5-E22-FQ1-A
Specifications of UPD44646363AF5-E22-FQ1-A
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UPD44646363AF5-E22-FQ1-A Summary of contents
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... The PD44646092A-A and PD44646093A-A are 8,388,608-word by 9-bit, the are 4,194,304-word by 18-bit and the double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. μ The PD44646xx2A-A is for 2.0 clock cycles and the μ μ ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Ordering Information 2.0 Clock Cycles Read Latency Part number Cycle Time ns Note μ PD44646092AF5-E25-FQ1-A 2.5 μ PD44646092AF5-E30-FQ1-A 3.0 μ PD44646092AF5-E33-FQ1-A 3.3 μ Note PD44646182AF5-E25-FQ1-A 2.5 μ PD44646182AF5-E30-FQ1-A 3.0 μ PD44646182AF5-E33-FQ1-A 3.3 Note ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Feature Differences between DDR II and DDR II+ Features Frequency (DLL/PLL ON) Organization Read Latency Write Latency Input Clocks (K, K#) Output Clocks (C, C#) Echo Clock Number ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Pin Configurations [ CQ DQ5 ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A CQ DQ9 DQ10 DQ11 F NC DQ12 ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A CQ NC/144M B NC DQ27 DQ18 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 DQ21 G NC DQ31 ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Pin Identification Symbol Type Synchronous Address Inputs: These inputs are registered and must meet the setup and hold A Input times around the rising edge of K. All transactions operate on a burst ...
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... PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Block Diagram Address A Register Add. K# Dec. K CLK Gen. DLL Control BWx# Logic LD# 8 Write Register Write Driver Memory Array Sense AMPs MUX x18/x36/x72 x18/x36/x72 Output Register Preliminary Data Sheet M19960EJ1V0DS x9/x18/x36 x9/x18/x36 DQx CQ# Output Buffer CQ QVLD ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Power-On Sequence in DDR II+ SRAM DDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. The following timing charts show the recommended power-on sequence. The ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A On-Die Termination (ODT) On-Die Termination (ODT) is enabled by setting ODT control pin to HIGH at power-on sequence. The ODT resistors (R ) are set to 0.6 x RQ, where ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Truth Table 2.0 Clock Cycles Read Latency μ μ [ PD44646092A-A], [ PD44646182A-A], [ Operation CLK L → H WRITE cycle Load address, input write data on consecutive K and K# rising edge ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Byte Write Operation μ μ [ PD44646092A-A], [ PD44646093A-A] Operation K L → H Write DQ0 to DQ8 – L → H Write nothing – Remarks HIGH LOW, ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Bus Cycle State Diagram Load, Count = 2 READ DOUBLE Count = Count + 2 NOP, Count = 2 Supply voltage provided Power UP Remarks 1. Bus cycle is terminated after burst count ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage V Output supply voltage V Input voltage Input / Output voltage Operating ambient temperature Storage temperature Caution Exposing the device to stress above those ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A DC Characteristics ( 70° Parameter Symbol Input leakage current I LI I/O leakage current I LO Operating supply current (Read cycle / Write ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Thermal Characteristics Parameter Thermal resistance from junction to ambient air Thermal characterization parameter from junction to the top center of the package surface Thermal resistance from junction to case 16 Symbol Substrate Airflow ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A AC Characteristics ( 70° Test Conditions (V = 1.8 ± 0 Input waveform (Rise / Fall time ≤ 0.3 ns) 1.25 V 0.75 ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Read and Write Cycle Parameter Symbol Clock Average Clock cycle time (K, K#) TKHKH Clock phase jitter (K, K#) TKC var Clock HIGH time (K, K#) TKHKL Clock LOW time (K, K#) TKLKH ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A slew rate must be less than 0 per 50 ns for DLL/PLL lock retention. DD DLL/PLL lock time begins once recommended that the device is kept ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Read and Write Timing 2.0 Clock Cycles Read Latency μ μ [ PD44646092A-A], [ PD44646182A-A], [ NOP READ READ (burst of 2) (burst TKHKH K TKHKL TKLKH TKHK#H ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A 2.5 Clock Cycles Read Latency μ μ [ PD44646093A-A], [ PD44646183A-A], [ NOP READ READ (burst of 2) (burst TKHKH K TKHKL TKLKH TKHK#H K# LD# TIVKH TKHIX ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Application Example SRAM LD SRAM Controller R Data IO Address LD BW# QVLD SRAM#1 CQ/CQ SRAM#4 CQ/CQ ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name Pin assignments TCK 2R Test Clock Input. All input are ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A JTAG AC Test Conditions Input waveform (Rise / Fall time ≤ 1 ns) 1 Output waveform 0.9 V Output load 24 Test Points Test Points Figure 2. External ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A JTAG AC Characteristics ( 70°C) A Parameter Symbol Clock Clock cycle time t THTH Clock frequency f TF Clock HIGH time t THTL Clock LOW time t TLTH Output time ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Scan Register Definition (1) Register name Instruction register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A SCAN Exit Order Bit Signal name Bump no. x9 x18 x36 ID ODT 1 6R QVLD ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A JTAG Instructions Instructions EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary- scan register cells at output pins are used to apply test vectors, while those at ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Output Pin States of CQ, CQ#, QVLD and DQ Instructions Control-Register Status EXTEST 0 1 IDCODE 0 1 SAMPLE SAMPLE 0 1 BYPASS 0 1 Remark The output pin statuses during ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Boundary Scan Register Status of Output Pins CQ, CQ#, QVLD and DQ Instructions SRAM Status EXTEST READ (Low-Z) NOP (High-Z) IDCODE READ (Low-Z) NOP (High-Z) SAMPLE-Z READ (Low-Z) NOP (High-Z) SAMPLE READ (Low-Z) ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A TAP Controller State Diagram 1 Test-Logic-Reset Run-Test / Idle Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A 32 Run-Test/Idle Update-IR Exit1-IR Shift-IR Exit2-IR Pause-IR Exit1-IR Shift-IR Capture-IR Select-IR-Scan Select-DR-Scan Run-Test/Idle Test-Logic-Reset Preliminary Data Sheet M19960EJ1V0DS ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Select-DR-Scan Run-Test/Idle Preliminary Data Sheet M19960EJ1V0DS Update-DR Exit1-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR Capture-DR 33 ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Package Drawing 165-PIN PLASTIC BGA(15x17) E INDEX MARK ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices μ PD44646092AF5-FQ1-A : 165-pin PLASTIC BGA (15 x 17), Lead free μ PD44646182AF5-FQ1-A ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A [MEMO] 36 Preliminary Data Sheet M19960EJ1V0DS ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A [MEMO] Preliminary Data Sheet M19960EJ1V0DS 37 ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A [MEMO] 38 Preliminary Data Sheet M19960EJ1V0DS ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in ...
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PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor, Renesas, IDT, NEC Electronics, and Samsung. • The information in this document is current as of ...