UPD44646183AF5-E25-FQ1 Renesas Electronics America, UPD44646183AF5-E25-FQ1 Datasheet - Page 11

• Manufacturer Part Number: UPD44646183AF5-E25-FQ1
• Description: SRAM DDRII 72MBIT 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44646183AF5-E25-FQ1

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II+
• Memory Size: 72M (4M x 18)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Truth Table
2.0 Clock Cycles Read Latency
[
2.5 Clock Cycles Read Latency
[
Remarks
μ
μ
WRITE cycle
Load address, input write data on
consecutive K and K# rising edge
READ cycle
Load address, read data on
consecutive K and K# rising edge
NOP (No operation)
Clock stop
WRITE cycle
Load address, input write data on
consecutive K and K# rising edge
READ cycle
Load address, read data on
consecutive K and K# rising edge
NOP (No operation)
Clock stop
PD44646092A-A], [
PD44646093A-A], [
1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A+0 refers to the address input during a WRITE or READ cycle.
7. It is recommended that K = K# when clock is stopped. This is not essential but permits most rapid restart
Operation
Operation
Remarks listed below are for both products with 2.0 and 2.5 Clock Cycles Read Latency.
K. All control inputs are registered during the rising edge of K.
A+1 refers to the next internal burst address in accordance with the burst sequence.
by overcoming transmission line charging symmetrically.
μ
PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A
μ
μ
PD44646182A-A], [
PD44646183A-A], [
Stopped
Stopped
L → H
L → H
L → H
L → H
L → H
L → H
CLK
CLK
Preliminary Data Sheet M19960EJ1V0DS
μ
μ
PD44646362A-A]
PD44646363A-A]
LD#
LD#
H
H
L
L
X
L
L
X
R,W#
R,W#
H
X
X
H
X
X
L
L
Data in
Data out
DQ = High-Z
Previous state
Data in
Data out
DQ = High-Z
Previous state
Output clock
Output clock
Output data
Output data
Input clock
Input clock
Input data
Input data
DQ
DQ
K#(t+2) ↑
K(t+1) ↑
Q
K(t+2) ↑
K(t+1) ↑
Q
D
D
A
A
A
A
(A+0)
(A+0)
(A+0)
(A+0)
K#(t+1) ↑
K#(t+2) ↑
K#(t+1) ↑
D
Q
D
Q
K(t+3) ↑
A
A
A
A
(A+1)
(A+1)
(A+1)
(A+1)
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