DS1249AB-85# Maxim Integrated Products, DS1249AB-85# Datasheet - Page 7
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DS1249AB-85#
Manufacturer Part Number
DS1249AB-85#
Description
IC NVSRAM 2048KBIT 85NS 32DIP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1249AB-85.pdf
(9 pages)
Specifications of DS1249AB-85#
Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Memory Size
2M (256K x 8)
Speed
85ns
Interface
Parallel
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-DIP Module (600 mil), 32-EDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
POWER-DOWN/POWER-UP TIMING
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
2.
3. t
4. t
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
7. If the
8. If
9. Each DS1249 has a built-in switch that disconnects the lithium source until the user first applies V
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
11. In a power-down condition the voltage on any pin may not exceed the voltage on V
12. t
13. t
14. DS1249 modules are recognized by Underwriters Laboratories (UL) under file E99151.
PARAMETER
V
V
V
V
V
PARAMETER
Expected Data Retention Time
CC
CC
CC
CC
CC
going low to the earlier of
Cycle 1, the output buffers remain in a high-impedance state during this period.
buffers remain in high-impedance state during this period.
the output buffers remain in a high-impedance state during this period.
The expected t
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
OE
WE
WP
DS
WR1
WR2
Fail Detect to
slew from V
slew from 0V to V
Valid to
Valid to End of Write Protection
WE
is measured from the earlier of
is specified as the logical AND of
= V
is high for a Read Cycle.
and t
and t
CE
CE
is low or the
IH
DH1
DH2
or V
high transition occurs prior to or simultaneously with the
CE
low transition occurs simultaneously with or latter than the
are measured from
are measured from
TP
and
IL
DR
. If
CE
to 0V
is defined as accumulative time in the absence of V
WE
OE
and
TP
WE
Inactive
= V
WE
low transition occurs prior to or simultaneously with the
CE
IH
Inactive
during write cycle, the output buffers remain in a high impedance state.
or
WE
CE
WE
CE
going high.
going high.
going high.
or
SYMBOL
SYMBOL
CE
WE
t
t
t
t
REC
and
t
t
DR
PD
PU
R
F
going high.
7 of 9
WE
. t
MIN
MIN
150
150
WP
10
is measured from the latter of
TYP
TYP
CC
WE
MAX
MAX
starting from the time power
125
WE
1.5
2
high transition, the output
(T
low transition in Write
A
: See Note 10)
UNITS
UNITS
CC
CE
years
ms
ms
µs
µs
µs
.
(T
low transition,
A
DS1249Y/AB
= +25°C)
CE
NOTES
NOTES
or
11
9
WE
CC
.