DS1243Y-120 Maxim Integrated Products, DS1243Y-120 Datasheet
DS1243Y-120
Specifications of DS1243Y-120
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DS1243Y-120 Summary of contents
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... DS1243Y-120+ 0°C to +70°C + Denotes a lead(Pb)-free/RoHS-compliant device. 64k NV SRAM with Phantom Clock PIN CONFIGURATION TOP VIEW A12 DQ0 DQ1 DQ2 GND PIN-PACKAGE TOP MARK 28 EMOD (0.720a) DS1243Y 28 EMOD (0.720a) DS1243Y-120 28 EMOD (0.720a) DS1243Y-150 28 EMOD (0.720a) DS1243Y-120 DS1243Y RST DS1243Y N. ...
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... DESCRIPTION The DS1243Y 64K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 8192 words by 8 bits) with a built-in real time clock. The DS1243Y has a self-contained lithium energy source and control circuitry, which constantly monitors V condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent corrupted data in both the memory and real time clock ...
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... RAM and disconnects the lithium energy source. Normal RAM operation can resume CC after V exceeds 4.5V. CC See “Conditions of Acceptability” at FRESHNESS SEAL Each DS1243Y is shipped from Dallas Semiconductor with its lithium energy source disconnected, insuring full energy capacity. When V source is enabled for battery backup operation. (Write Enable) is inactive (high) and WE and OE ...
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... Write Enable ( OE control of the Phantom Clock starts the pattern recognition sequence by control of the SmartWatch. These 64 write cycles are used only to gain Initially, a read cycle to any memory WE DS1243Y ...
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... PHANTOM CLOCK REGISTER DEFINITION Figure 1 NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB DS1243Y ...
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... Registers and 6 contain one or more bits that always read logic 0. When writing these locations, either a logic acceptable. and oscillator functions. Bit 4 controls the RESET bit is set to logic 1, the RESET pin will cause the Phantom Clock to abort data transfer RESET input pin is ignored. When the DS1243Y RESET ...
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... Input Capacitance Input/Output Capacitance SYMBOL MIN TYP V 4 -0.3 IL SYMBOL MIN TYP 5.0 CCS1 I 3.0 CCS2 I CC01 V 4.25 TP SYMBOL MIN TYP I DS1243Y MAX UNITS NOTES 5 +0 +0.8 V MAX UNITS NOTES A +1.0 12 4.5 V MAX UNITS NOTES ...
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... DS Data Hold Time from TEST CONDITIONS Output Load: 50pF + 1TTL Gate Input Pulse Levels Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns DS1243Y-120 DS1243Y-150 MIN MAX MIN MAX 120 150 120 150 60 70 120 ...
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... SYMBOL MIN t 120 COE t 10 OEE ODO 120 WC t 100 100 CW t 200 RST t PF SYMBOL MIN 300 ) REC SYMBOL MIN DS1243Y TYP MAX UNITS NOTES ns 100 ns 100 TYP MAX UNITS NOTES s s TYP MAX UNITS NOTES years ...
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... MEMORY READ CYCLE (NOTE 1) MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND DS1243Y ...
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... MEMORY WRITE CYCLE 2 (NOTES 2 AND 8) RESET FOR PHANTOM CLOCK READ CYCLE TO PHANTOM CLOCK DS1243Y ...
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... WRITE CYCLE TO PHANTOM CLOCK POWER-DOWN/POWER-UP CONDITION DS1243Y ...
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NOTES high for a read cycle specified as the logical AND of WP going low to the earlier ...