UPD44164362AF5-E33-EQ2 Renesas Electronics America, UPD44164362AF5-E33-EQ2 Datasheet - Page 13

• Manufacturer Part Number: UPD44164362AF5-E33-EQ2
• Description: SRAM DDRII 18MBIT CIO 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44164362AF5-E33-EQ2

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Burst Sequence
Linear Burst Sequence Table
[
Truth Table
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
μ
External Address
1st Internal Burst Address
WRITE cycle
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Load address, read data on two
consecutive C and C# rising edge
NOP (No operation)
Clock stop
PD44164182A-A,
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst
7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
Operation
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
K. All control inputs are registered during the rising edge of K.
address in accordance with the linear burst sequence.
rapid restart by overcoming transmission line charging symmetrically.
μ
PD44164362A-A]
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
A0
0
1
LD# R, W#
H
X
L
L
H
L
X
X
Data Sheet M19866EJ1V0DS
Stopped
L → H
L → H
L → H
CLK
A0
1
0
Previous state
Data out
Data in
High-Z
DQ
Output clock
Output data
Input clock
Input data
C#(t+1) ↑
K(t+1) ↑
D(A1)
Q(A1)
K#(t+1) ↑
C(t+2) ↑
Q(A2)
D(A2)
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