SST25WF080-75-4I-SAF Microchip Technology, SST25WF080-75-4I-SAF Datasheet
SST25WF080-75-4I-SAF
Specifications of SST25WF080-75-4I-SAF
Related parts for SST25WF080-75-4I-SAF
SST25WF080-75-4I-SAF Summary of contents
Page 1
... Erase or Program operation is less than alternative flash memory technologies. The SST25WF080 is offered in both an 8-lead, 150 mils SOIC package and an 8-bump XFBGA package. See Fig- ures 2 and 3 for the pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...
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... See “End-of-Write Detection” on page 12 for more information. FIGURE 1: Functional Block Diagram ©2010 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# RST#/HOLD# 2 8Mbit 1.8V SPI Serial Flash SST25WF080 SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1203 F01.0 S71203-03-000 04/10 ...
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... To reset the operation of the device and the internal logic. The device powers on with RST# pin functionality as default. To temporarily stop serial communication with SPI Flash memory while device is selected. This is selected by an instruction sequence; see “Reset/Hold Mode” on page 5. To provide power supply voltage: 1.65-1.95V for SST25WF080 3 Advance Information T1.0 1203 ...
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... FIGURE 4: SPI Protocol ©2010 Silicon Storage Technology, Inc. 8Mbit 1.8V SPI Serial Flash The SST25WF080 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 4, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... SPI Serial Flash SST25WF080 Reset/Hold Mode The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected option where an Enable-Hold instruction enables the Hold mode ...
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... HOLD# Active FIGURE 6: Hold Condition Waveform Write Protection SST25WF080 provide software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register pro- vide Write protection to the memory array and the status register ...
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... SPI Serial Flash SST25WF080 Status Register The software status register provides status on whether the flash memory array is available for any Read or Write oper- ation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or ...
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... Chip-Erase can only be executed if Block-Protection bits are all ‘0’. After power-up, BP3, BP2, BP1 and BP0 are set to defaults. See Table 4 for defaults at power-up. TABLE 5: Software Status Register Block Protection for SST25WF080 Protection Level None 1 (Upper 16th Memory, Blocks 30 and 31) ...
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... Sector-Erase, Block-Erase, Write-Sta- tus-Register, or Chip-Erase instructions. The complete instructions are provided in Table 6. All instructions are syn- chronized off a high-to-low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most TABLE 6: Device Operation Instructions for SST25WF080 Instruction Description Read Read Memory ...
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... For example, for 2 Mbit den- sity, once the data from address location 7FFFFH is read, the next output will be from address location 000000H ADD. ADD. ADD MSB 10 8Mbit 1.8V SPI Serial Flash SST25WF080 -A . CE# must N+1 N+2 N+3 N+4 D OUT D D ...
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... SPI Serial Flash SST25WF080 Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. ...
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... RDSR command can poll the status of the Software Status Register. This is shown in Figure 11 Following the with CE FIGURE 10: Enable SO as Hardware RY/BY# FIGURE 11: Disable SO as Hardware RY/BY# 12 8Mbit 1.8V SPI Serial Flash SST25WF080 CE# MODE SCK MODE MSB SO HIGH IMPEDANCE 1203 F09.0 during AAI Programming CE# MODE SCK MODE 0 ...
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... SPI Serial Flash SST25WF080 CE MODE 3 SCK MODE Load AAI command, Address, 2 bytes data SO Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming FIGURE 12: Auto Address Increment (AAI) Word Program Sequence ...
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... Busy bit in the software status register or wait T completion of the internal self-timed Block-Erase. See Fig- ure 15 for the Block-Erase sequences ADDR ADDR MSB MSB HIGH IMPEDANCE 14 8Mbit 1.8V SPI Serial Flash SST25WF080 ), remaining address bits can for the completion of the internal self-timed ADD. 1203 F13 Address bits [ ...
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... SPI Serial Flash SST25WF080 64-KByte Block-Erase The Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area is ignored. Prior to any Write oper- ation, the Write-Enable (WREN) instruction must be exe- cuted. CE# must remain active low for the duration of any command sequence ...
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... CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed. See Figure 19 for the WREN instruction sequence. CE# MODE SCK MODE MSB SO HIGH IMPEDANCE 1203 F18.0 16 8Mbit 1.8V SPI Serial Flash SST25WF080 Status 1203 F17.0 S71203-03-000 04/10 ...
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... SPI Serial Flash SST25WF080 Write-Disable (WRDI) The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit and AAI to 0 disabling any new Write operations from occurring. The WRDI instruction will not terminate any programming operation in progress. Any FIGURE 20: Write Disable (WRDI) Sequence ...
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... Enable-Hold FIGURE 22: Enable-Hold Sequence Read-ID The Read-ID instruction identifies the manufacturer as SST and the device as SST25WF080. Use the Read-ID instruc- tion to identify SST device when using multiple manufactur- ers in the same socket. See Table 7. The device information is read by executing an 8-bit com- mand, 90H or ABH, followed by address bits [A lowing the Read-ID instruction, the manufacturer’ ...
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... SST25WF080 JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25WF080 and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin ...
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... Output shorted for no more than one second. No more than one output shorted at a time. Operating Range Range Ambient Temp Industrial -40°C to +85°C ©2010 Silicon Storage Technology, Inc. = 25° 1. Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . . Output Load . . . . . . . . . . . . . . . . . . . . . C 1.65-1.95V 20 8Mbit 1.8V SPI Serial Flash SST25WF080 +0.5V DD +2. S71203-03-000 04/10 ...
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... SPI Serial Flash SST25WF080 Power-Up Specifications All functionalities and DC specifications are specified for less than 180 ms). If the VDD ramp rate is slower than 1V/100 ms, a hardware reset is required. The recom- mended V power-up to RESET# high time should be greater than 100 µs to ensure a proper reset. See Table 9 DD and Figures 25 and 26 for more information ...
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... Advance Information Max DD Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. V Min DD FIGURE 26: Power-up Timing Diagram ©2010 Silicon Storage Technology, Inc. 8Mbit 1.8V SPI Serial Flash T PU-READ T Device fully accessible PU-WRITE 22 SST25WF080 Time 1203 F27.0 S71203-03-000 04/10 ...
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... SPI Serial Flash SST25WF080 DC Characteristics TABLE 10: DC Operating Characteristics Symbol Parameter I Read Current DDR I Read Current DDR2 I Program and Erase Current DDW I Standby Current SB I Input Leakage Current LI I Output Leakage Current LO V Input Low Voltage IL V Input High Voltage ...
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... Relative to SCK 3. AAI-Word Program T maximum specification is also at 25 µs maximum time BP ©2010 Silicon Storage Technology, Inc. 8Mbit 1.8V SPI Serial Flash Limits - 33 MHz Limits - 75 MHz Min Max Min 0.1 0 SST25WF080 Max Units 75 MHz ns ns 0.1 v/ns 0.1 v/ µs T13.2 1203 S71203-03-000 04/10 ...
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... SPI Serial Flash SST25WF080 CE# T CES T CHH SCK T DS MSB SI HIGH-Z SO FIGURE 27: Serial Input Timing Diagram CE# T SCKH SCK T CLZ SO SI FIGURE 28: Serial Output Timing Diagram ©2010 Silicon Storage Technology, Inc SCKR T SCKL T OH MSB Advance Information T CPH T CHS ...
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... REFERENCE POINTS for a logic ‘1’ and V (0.1V ) for a logic ‘0’. Measurement reference points for DD ILT DD ) and V (0.4V ). Input rise and fall times (10 8Mbit 1.8V SPI Serial Flash SST25WF080 T HHS T LZ 1203 F26 OUTPUT V LT 1203 F28.0 ↔ 90%) are <5 ns. Note ...
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... SST 25 WF XXX - XXX - XX Valid combinations for SST25WF080 SST25WF080-75-4I-SAF SST25WF080-75-4I-ZAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2010 Silicon Storage Technology, Inc ...
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... Note: For more information about the ZA package, including a copy of the package diagram, please contact your SST representative. ©2010 Silicon Storage Technology, Inc. 8Mbit 1.8V SPI Serial Flash SIDE VIEW 7° 4 places 0.51 0.33 1.27 BSC END VIEW 45° 0.25 0.10 1.75 0.25 1.35 0.19 08-soic-5x6-SA-8 28 SST25WF080 7° 4 places 0° 8° 1.27 0.40 1mm S71203-03-000 04/10 ...
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... SPI Serial Flash SST25WF080 TABLE 14: Revision History Number 00 • Initial release of data sheet 01 • Revised Active Read Current, Standby Current, Chip-Erase Time, and Sector-/ Block-Erase Time in Features on page 1 • Added a footnote to Table 2 Reset Timing Parameters • Revised Table 6 on page 9 • ...