CY7C09159AV-12AC Cypress Semiconductor Corp, CY7C09159AV-12AC Datasheet - Page 4

• Manufacturer Part Number: CY7C09159AV-12AC
• Description: IC SRAM 72KBIT 12NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09159AV-12AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 72K (8K x 9)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1177

Pin Definitions
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65 C to +150 C
Ambient Temperature with Power Applied ..–55 C to +125 C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V
DC Input Voltage......................................–0.5V to V
Note:
Document #: 38-06053 Rev. *A
4.
5.
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
OE
R/W
FT/PIPE
GND
NC
V
0L
CC
Left Port
0L
0L
L
The voltage on any input or I/O pin can not exceed the power pin during power-up
Industrial parts are available in CY7C09169AV only.
–A
L
L
L
–I/O
,CE
13L
L
L
1L
L
8L
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
OE
R/W
FT/PIPE
Right Port
0R
0R
0R
R
–A
R
R
R
–I/O
,CE
13R
R
R
[4]
R
1R
8R
Address Inputs (A
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address counter
with data present on the I/O pins.
Chip Enable Input. To select either the left or right port, both CE
their active states (CE
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual-port memory array.
For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
0
A
CC
CC
12
0
+0.5V
+0.5V
for 8K; A
V
0
IL
–I/O
and CE
7
0
for x8 devices; I/O
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
Latch-Up Current..................................................... >200 mA
Operating Range
A
Commercial
Industrial
13
1
for 16K devices).
V
Range
Description
IH
).
[5]
0
–I/O
8
–40 C to +85 C
Temperature
0 C to +70 C
for x9 devices).
Ambient
0
AND CE
CY7C09159AV
CY7C09169AV
1
must be asserted to
3.3V
3.3V
Page 4 of 17
V
MAX.
CC
300 mV
300 mV