M29DW641F70N6F NUMONYX, M29DW641F70N6F Datasheet - Page 16

• Manufacturer Part Number: M29DW641F70N6F
• Description: IC FLASH 64MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29DW641F70N6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bus Operations
3
3.1
3.2
3.3
3.4
16/80
Bus Operations
There are five standard Bus Operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
Dual Operations are possible in the M29DW641F, thanks to their multiple bank architecture.
While programming or erasing in one banks, Read Operations are possible in any of the
other banks. Write Operations are only allowed in one bank at a time.
See
Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by the
memory and do not affect Bus Operations.
Bus Read
Bus Read Operations read from the memory cells, or specific registers in the Command
Interface. To speed up the Read Operation the memory array can be read in Page mode
where data is internally read and stored in a page buffer. The Page has a size of 8 Words
and is addressed by the address inputs A0-A2.
A valid Bus Read Operation involves setting the desired address on the Address Inputs,
applying a Low signal, V
High, V
waveforms
for details of when the output becomes valid.
Bus Write
Bus Write Operations write to the Command Interface. A valid Bus Write Operation begins
by setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write Operation. See
and
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply current to
the Standby Supply current, I
Standby current level see
During program or Erase Operations the memory will continue to use the Program/Erase
Supply current, I
Table 21
Table 3: Bus Operations
IH
. The Data Inputs/Outputs will output the value, see
,
Figure 12: Page Read AC waveforms
and
CC3
Table 22
, for Program or Erase Operations until the operation completes.
IL
, to Chip Enable and Output Enable and keeping Write Enable
Table 19: DC characteristics
, Write AC Characteristics, for details of the timing requirements.
, for a summary. Typically glitches of less than 5ns on Chip
IH
CC2
, the memory enters Standby mode and the Data
, Chip Enable should be held within V
Figure 13
, and
and
.
Table 20: Read AC characteristics
Figure 14
Figure 11: Random Read AC
, Write AC Waveforms,
CC
± 0.2V. For the
M29DW641F
IH
IH
,
,
.