M29W400DB55N6E NUMONYX, M29W400DB55N6E Datasheet - Page 13

• Manufacturer Part Number: M29W400DB55N6E
• Description: IC FLASH 4MBIT 55NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W400DB55N6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 4M (512K x 8 or 256K x 16)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Access Time: 55ns
• Memory: RoHS Compliant
• Memory Configuration: 512K X 8, 256K X 16
• Interface Type: Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2
2.1
2.2
2.3
2.4
2.5
2.6
Signal descriptions
See
this device.
Address inputs (A0-A17)
The Address inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the command
interface of the Program/Erase controller.
Data inputs/outputs (DQ0-DQ7)
The Data inputs/outputs output the data stored at the selected address during a Bus Read
operation. During Bus Write operations they represent the commands sent to the command
interface of the Program/Erase controller.
Data inputs/outputs (DQ8-DQ14)
The Data inputs/outputs output the data stored at the selected address during a Bus Read
operation when BYTE is High, V
high impedance. During Bus Write operations the Command Register does not use these
bits. When reading the Status Register these bits should be ignored.
Data input/output or Address input (DQ15A-1)
When BYTE is High, V
BYTE is Low, V
the word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data input/output to include this pin when BYTE is High and
references to the Address inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
Figure 1: Logic
IL
, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of
diagram, and
IH
, this pin behaves as a Data input/output pin (as DQ8-DQ14). When
IH
. When BYTE is Low, V
Table :
, for a brief overview of the signals connected to
IH
, all other pins are ignored.
IL
, these pins are not used and are
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