M29W400FB55N3F NUMONYX, M29W400FB55N3F Datasheet - Page 6

• Manufacturer Part Number: M29W400FB55N3F
• Description: IC FLASH 4MBIT 55NS 3V 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W400FB55N3F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 4M (512K x 8 or 256K x 16)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
6/56
Description
The M29W800FT/B and M29W400FT/B are 8-Mbit (1 Mbit × 8 or 512 Kbit × 16) and 4-Mbit
(512 Kbit × 8 or 256 Kbit × 16) non-volatile memory devices that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (2.7 V to 3.6
V) supply. On power-up the memory defaults to its read mode where it can be read in the
same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the command interface of the memory. An on-chip
program/erase controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, see
800FT/B(× 8)
have been divided into four additional blocks. The 16-Kbyte boot block can be used for
small initialization code to start the microprocessor, the two 8-Kbyte parameter blocks can
be used for parameter storage and the remaining 32-Kbyte is a small main block where the
application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12 × 20 mm) and TFBGA48 6 × 8 mm (0.8 mm pitch)
packages. The memory is supplied with all the bits erased (set to ’1’).
Figure 1.
Logic diagram
and
Figure 7: Block addresses, 800FT/B(×
A0-A18
BYTE
RP
W
G
E
19
V CC
V SS
15
16). The first or last 64 Kbytes
DQ0-DQ14
DQ15A–1
RB
Figure 6: Block addresses,
AI13852