M25PX32-VZM6F NUMONYX, M25PX32-VZM6F Datasheet - Page 33

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M25PX32-VZM6F

Manufacturer Part Number
M25PX32-VZM6F
Description
IC FLASH 32MBIT 75MHZ 24TBGA
Manufacturer
NUMONYX
Series
Forté™r
Datasheet

Specifications of M25PX32-VZM6F

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
32M (4M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25PX32-VZM6FTR

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6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a
maximum frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 14. Read Data Bytes (READ) instruction sequence and data-out sequence
1. Address bits A23 to A22 are Don’t care.
DQ0
DQ1
S
C
0
1
High Impedance
2
Instruction
3
R
, during the falling edge of Serial Clock (C).
4
5
6
7
MSB
23
8
22 21
Figure
9 10
24-bit address
14.
3
28 29 30 31 32 33 34 35
2
1
0
MSB
7
6
5
Data Out 1
4
3
36 37 38
2
1
39
0
Data Out 2
7
AI13736
33/68

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