M25PX32-VMP6F NUMONYX, M25PX32-VMP6F Datasheet - Page 31

• Manufacturer Part Number: M25PX32-VMP6F
• Description: IC FLASH 32MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PX32-VMP6F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PX32-VMP6FTR

6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (DQ0).
The instruction sequence is shown in
The Write Status Register (WRSR) instruction has no effect on b6, b1 and b0 of the Status
Register. b6 is always read as ‘0’.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is t
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in
the user to set and reset the Status Register Write Disable (SRWD) bit in accordance with
the Write Protect (W/V
Protect (W/V
The Write Status Register (WRSR) instruction is not executed once the hardware protected
mode (HPM) is entered.
Figure 13. Write Status Register (WRSR) instruction sequence
S
C
DQ0
DQ1
PP
) signal allow the device to be put in the hardware protected mode (HPM).
PP
Table
) signal. The Status Register Write Disable (SRWD) bit and Write
0
1
High Impedance
3. The Write Status Register (WRSR) instruction also allows
2
Instruction
3
4
Figure
5
6
13.
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
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W
) is
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