M29W800DB70ZE6F NUMONYX, M29W800DB70ZE6F Datasheet

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... Electronic signature – Manufacturer code: 0020h – Top device code M29W800DT: 22D7h – Bottom device code M29W800DB: 225Bh April 2009 8-Mbit (1 Mbit 512 Kbits x 16, boot block) Rev 11 M29W800DT M29W800DB 3 V supply flash memory SO44 (M) TSOP48 ( FBGA TFBGA48 (ZE www.numonyx.com 1/52 1 ...

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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 Chip Erase ...

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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in SO44, TSOP48 ( mm) and TFBGA48 (0.8 mm pitch) packages. The memory is supplied with all the bits erased (set to ’1’). Figure 1. ...

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Table 1. Signal names Signal A0-A18 Address inputs DQ0-DQ7 Data inputs/outputs DQ8-DQ14 Data inputs/outputs DQ15A–1 Data input/output or address input E Chip enable G Output enable W Write enable RP Reset/block temporary unprotect RB Ready/busy output (not available on SO44 ...

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Figure 3. TSOP connections 8/52 A15 1 48 A14 A13 A12 A11 A10 M29W800DT M29W800DB A18 A17 AI05461 ...

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Figure 4. TFBGA connections (top view through package A17 DQ0 DQ8 G G DQ9 DQ1 ...

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Figure 5. Block addresses (x 8) M29W800DT Top boot block addresses (x 8) FFFFFh 16 Kbyte FC000h FBFFFh 8 Kbyte FA000h F9FFFh 8 Kbyte F8000h F7FFFh 32 Kbyte F0000h EFFFFh 64 Kbyte E0000h 1FFFFh 64 Kbyte 10000h 0FFFFh 64 Kbyte ...

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Figure 6. Block addresses (x 16) M29W800DT Top boot block addresses (x 16) 7FFFFh 8 Kword 7E000h 7DFFFh 4 Kword 7D000h 7CFFFh 4 Kword 7C000h 7BFFFh 16 Kword 78000h 77FFFh 32 Kword 70000h 0FFFFh 32 Kword 08000h 07FFFh 32 Kword ...

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... BYTE is Low except when stated explicitly otherwise. 2.5 Chip enable (E) The chip enable, E, activates the memory, allowing bus read and bus write operations to be performed. When Chip Enable is High, V 2.6 Output enable (G) The output enable, G, controls the bus read operation of the memory. ...

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... Write enable (W) The write enable, W, controls the bus write operation of the memory’s command interface. 2.8 Reset/block temporary unprotect (RP) The reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. ...

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A 0.1 μF capacitor should be connected between the V ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I 2.12 ...

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... Enable are ignored by the memory and do not affect bus operations. 3.1 Bus read Bus read operations read from the memory cells, or specific registers in the command interface. A valid bus read operation involves setting the desired address on the address inputs, applying a Low signal, V Enable High, V ...

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... They require V applied to some pins. 3.6.1 Electronic signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in and 3, Bus operations. ...

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... From the auto select mode the manufacturer code can be read using a bus read operation with and manufacturer code for Numonyx is 0020h. The device code can be read using a bus read operation with other address bits may be set to either V 22D7h and for the M29W800DB is 225Bh. ...

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... Note that the Program command cannot change a bit set to ’0’ back to ’1’. One of the erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 4.4 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory ...

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... When an error occurs the memory will continue to output the status register. A Read/Reset command must be issued to reset the error condition and return to read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 4.8 Block Erase command The Block Erase command can be used to erase a list of one or more blocks ...

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... Read CFI Query command The Read CFI Query command is used to read data from the common flash interface (CFI) memory area. This command is valid when the device is in the read array mode, or when the device is in auto select mode. One bus write cycle is required to issue the Read CFI Query command. Once the command is issued subsequent bus read operations read from the common flash interface memory area ...

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Table 4. Commands, 16-bit mode, BYTE = V Command Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 X Read/Reset 3 555 Auto Select 3 555 Program 4 555 Unlock Bypass 3 555 Unlock Bypass Program ...

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Table 5. Commands, 8-bit mode, BYTE = V Command Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 X Read/Reset 3 AAA Auto Select 3 AAA Program 4 AAA Unlock Bypass 3 AAA Unlock Bypass 2 ...

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... DQ7, not its complement. During erase operations the data polling bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the erase operation the memory returns to read mode. In erase suspend mode the data polling bit will output a ’1’ during a bus read operation within a block being erased. The data polling bit will change from a ’ ...

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... Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting will set DQ5 to ‘1’. A bus read operation to that address will show the bit is still ‘0’. One of the erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’ ...

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Table 7. Status register bits Operation Address Program Any address Program during erase Any address suspend Program error Any address Chip erase Any address Erasing block Block erase before timeout Non-erasing block Erasing block Block erase Non-erasing block Erasing block ...

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Figure 8. Data toggle flowchart 26/52 START READ DQ6 READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI01370C ...

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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Refer also to the Numonyx SURE program and other relevant quality documents. ...

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DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement ...

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Figure 10. AC measurement load circuit V CC 0.1µ includes JIG capacitance Table 10. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 11. DC characteristics Symbol Parameter ...

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Figure 11. Read mode AC waveforms A0-A18/ A– DQ0-DQ7/ DQ8-DQ15 BYTE tELBL/tELBH Table 12. Read AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC ...

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Figure 12. Write AC waveforms, write enable controlled A0-A18/ A–1 E tELWL G tGHWL W DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB Table 13. Write AC characteristics, write enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...

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Figure 13. Write AC waveforms, chip enable controlled A0-A18/ A–1 W tWLEL G tGHEL E DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB Table 14. Write AC characteristics, chip enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...

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Figure 14. Reset/block temporary unprotect AC waveforms tPLPX RP Table 15. Reset/block temporary unprotect AC characteristics Symbol Alt (1) t PHWL RP High to Write Enable Low, Chip Enable t t PHEL RH Low, Output Enable ...

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... Package mechanical data In order to meet environmental requirements, Numonyx offers these devices in RoHS packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 15. SO44 – ...

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Table 16. SO44 – 44 lead plastic small outline, 525 mils body width, package mechanical data millimeters Symbol Typ 2.30 b 0. 28.20 E 13.30 EH 16.00 e 1. ...

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Figure 16. TSOP48 – 48 lead plastic thin small outline mm, package outline DIE 1. Drawing is not to scale. Table 17. TSOP48 – 48 lead plastic thin small outline ...

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Figure 17. TFBGA48 – ball array – 0.80 mm pitch, bottom view package outline FD FE BALL "A1" Drawing is not to scale. Table 18. TFBGA48 ...

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... Option T = tape & reel packing E = lead-free package, standard packing F = lead-free package, tape & reel packing Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 38/52 M29W800DB ...

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Appendix A Block address table Table 20. Top boot block addresses, M29W800DT # Size (Kbytes ...

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Table 21. Bottom boot block addresses, M29W800DB # Size (Kbytes ...

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... The CFI data structure also contains a security area where a 64-bit unique security number is written (see Table 27: Security code by the final user impossible to change the security number after it has been written by Numonyx. Issue a Read command to return to read mode. Table 22. Query structure overview Address ...

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Table 23. CFI query identification string Address 10h 20h 0051h 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h 14h 28h 0000h 15h 2Ah 0040h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 0000h 19h 32h ...

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Table 25. Device geometry definition Address Data 27h 4Eh 0014h Device size = 2 28h 50h 0002h Flash device interface code description 29h 52h 0000h 2Ah 54h 0000h Maximum number of bytes in multi-byte program or ...

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Table 26. Primary algorithm-specific extended query table Address 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h Table 27. ...

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... Unlike the command interface of the program/erase controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example, the techniques for AMD parts will not work on Numonyx parts. Care should be taken when changing drivers for one part to work on another. ...

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Table 28. Programmer technique bus operations, BYTE = V Operation E G Block protect Chip unprotect Block protection verify Block unprotection verify 46/52 Address ...

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Figure 18. Programmer equipment block protect flowchart ADDRESS = BLOCK ADDRESS START Wait 4µ Wait 100µ ...

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Figure 19. Programmer equipment chip unprotect flowchart NO 48/52 START PROTECT ALL BLOCKS CURRENT BLOCK = 0 A6, A12, A15 = Wait 4µ Wait ...

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Figure 20. In-system equipment block protect flowchart ADDRESS = BLOCK ADDRESS ADDRESS = BLOCK ADDRESS ...

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Figure 21. In-system equipment chip unprotect flowchart ISSUE READ/RESET 50/52 START PROTECT ALL BLOCKS CURRENT BLOCK = WRITE 60h ANY ADDRESS WITH ...

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... Figure 2: SO connections speed class added. Removed TFBGA48 (ZA mm) package. Converted to new ST 8 corporate template. 9 Applied Numonyx branding. 10 Minor text changes. Revised Chip Erase signal value (maximum) in times and program/erase endurance cycles 11 Revised Block Erase (64-Kbytes) signal value (maximum) in Program/erase times and program/erase endurance cycles seconds ...

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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...