M45PE80-VMP6TG NUMONYX, M45PE80-VMP6TG Datasheet - Page 18

• Manufacturer Part Number: M45PE80-VMP6TG
• Description: IC FLASH 8MBIT 50MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 12ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 4mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE80-VMP6TG; M45PE80-VMP6TGTR

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Write Enable (WREN)
The Write Enable (WREN) instruction
The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page
Program (PP), Page Erase (PE), and Sector Erase (SE) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 6.
Write Disable (WRDI)
The Write Disable (WRDI) instruction
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Figure 7.
Power-up
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
Write Enable (WREN) instruction sequence
Write Disable (WRDI) instruction sequence
S
C
D
Q
S
C
D
Q
High Impedance
0
(Figure
(Figure
High Impedance
1
0
2
1
Instruction
3
2
7) resets the Write Enable Latch (WEL) bit.
6) sets the Write Enable Latch (WEL) bit.
Instruction
4
3
5
4
6
5
7
6
7
AI02281E
AI03750D