M24C64-WBN6P STMicroelectronics, M24C64-WBN6P Datasheet - Page 6

• Manufacturer Part Number: M24C64-WBN6P
• Description: IC EEPROM 64KBIT 400KHZ 8DIP
• Manufacturer: STMicroelectronics

Specifications of M24C64-WBN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 8 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Memory Organization: 8K X 8
• Clock Speed: 400MHz
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Ic Generic Number: 24C64
• Memory Voltage, Vcc: 2.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8575; M24C64-WBN6P

Description
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Description
M24C64-x and M24C64-DF devices are I2C-compatible electrically erasable programmable
memories (EEPROM). They are organized as 8192 × 8 bits.
The M24C64-D also offers an additional page, named the Identification Page (32 bytes)
which can be written and (later) permanently locked in Read-only mode. This Identification
Page offers flexibility in the application board production line, as it can be used to store
unique identification parameters and/or parameters specific to the production line.
Figure 1.
I
devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I
bus definition.
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
2
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
Logic diagram
Table
Doc ID 16891 Rev 23
2), terminated by an acknowledge bit.
2
C protocol, with all memory operations synchronized
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
th
2
bit
C