M25P16-VMN6TP NUMONYX, M25P16-VMN6TP Datasheet - Page 13

IC FLASH 16MBIT 75MHZ 8SOIC

M25P16-VMN6TP

Manufacturer Part Number
M25P16-VMN6TP
Description
IC FLASH 16MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet

Specifications of M25P16-VMN6TP

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
16M (2M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Package
8SOIC N
Cell Type
NOR
Density
16 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 32
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P16-VMN6TP
M25P16-VMN6TPTR

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4.5
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See
detailed description of the Status Register bits.
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P16 features the following data protection mechanisms:
Power on reset and an internal timer (t
changes while the power supply is outside the operating specification
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
Software Protected Mode (SPM): The Block Protect bits (BP2, BP1, BP0) allow part of
the memory to be configured as read-only.
Hardware Protected Mode (HPM): The Write Protect (W) signal allows the Block
Protect bits (BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) to be
protected.
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all Write, Program and Erase instructions are ignored.
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Section 6.4: Read Status Register (RDSR)
PUW
) can provide protection against inadvertent
for a
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