M45PE20-VMP6G NUMONYX, M45PE20-VMP6G Datasheet - Page 31

IC FLASH 2MBIT 75MHZ 8VFQFPN

M45PE20-VMP6G

Manufacturer Part Number
M45PE20-VMP6G
Description
IC FLASH 2MBIT 75MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r

Specifications of M45PE20-VMP6G

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Memory Configuration
256K X 8
Ic Interface Type
Serial, SPI
Clock Frequency
25MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
VDFPN
No. Of Pins
8
Interface Type
Serial, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
M45PE20-VMP6G
Manufacturer:
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Part Number:
M45PE20-VMP6G
Manufacturer:
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Quantity:
20 000
M45PE20
6.12
Release from deep power-down (RDP)
Once the device has entered the deep power-down mode, all instructions are ignored
except the release from deep power-down (RDP) instruction. Executing this instruction
takes the device out of the deep power-down mode.
The release from deep power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on serial data input (D). Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in
The release from deep power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, t
standby power mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any release from deep power-down (RDP) instruction, while an erase, program or write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Release from deep power-down (RDP) instruction sequence
S
C
D
Q
High Impedance
0
1
2
Instruction
3
4
5
6
Figure
7
17.
Deep power-down mode
t
RDP
RDP
, the device is put in the
Standby mode
Instructions
AI06807
31/47

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