M25P80-VMW6G NUMONYX, M25P80-VMW6G Datasheet - Page 14

• Manufacturer Part Number: M25P80-VMW6G
• Description: IC FLASH 8MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P80-VMW6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Ic Interface Type: Serial, SPI
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Memory Configuration: 1M X 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Table 2.
1. The device is ready to accept a Bulk Erase instruction only if all Block Protect bits (BP2, BP1, BP0) are 0.
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low. The Hold
condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low (as shown in
rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C)
being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
BP2
Status Register
bit
1
1
1
1
content
BP1
bit
0
0
1
1
Protected area sizes
BP0
bit
0
1
0
1
Upper half (eight sectors: 8 to 15)
All sectors (sixteen sectors: 0 to 15)
All sectors (sixteen sectors: 0 to 15)
All sectors (sixteen sectors: 0 to 15)
Figure 5: Hold condition
Protected area
Figure
Memory content
activation).
5). The Hold condition ends on the
Lower half (eight sectors: 0 to 7)
none
none
none
Unprotected area