M25PE40-VMP6TG NUMONYX, M25PE40-VMP6TG Datasheet - Page 60
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M25PE40-VMP6TG
Manufacturer Part Number
M25PE40-VMP6TG
Description
IC FLASH 4MBIT 75MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25PE40-VMN6TP.pdf
(62 pages)
Specifications of M25PE40-VMP6TG
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25PE40-VMP6TG
M25PE40-VMP6TGTR
M25PE40-VMP6TGTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25PE40-VMP6TG
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
M25PE40-VMP6TG
Manufacturer:
MICRON
Quantity:
20 000
Revision history
14
60/62
Revision history
Table 29.
09-Nov-2004
01-Dec-2004
11-Aug 2006
01-Apr-2004
11-Jan-2005
4-Oct-2005
Date
Document revision history
Revision
0.1
1
2
3
4
5
Initial release.
Write Protect (W) pin replaced by Top Block Lock (TBL).
Section 2.5: Reset (Reset)
modified. Reset timings t
Table 20: AC characteristics (33 MHz operation)
Table 21: Reset timings
promoted from target specification to preliminary data.
Top Block Lock (TBL) renamed as Top Sector Lock (TSL). Small text
changes. Deep Power-down mode clarified in
Power, Standby Power and Deep Power-down
Notes removed from
Wording changes. SO16 package removed, SO8 wide package
added.
Added
status promoted from preliminary data to full datasheet.
AC characteristics (25 MHz operation)
easy way to modify
Section 6.9: Page Write (PW)
updated to explain optimal use of Page Write and Page Program
instructions. Clock slew rate changed from 0.03 to 0.1 V/ns.
Updated
ECOPACK® information.
Changed document to new template; amended figure in Feature
summary; replaced
the SPI
of
package no lead 6 × 5 mm, package outline
amended name of the MP package in
information
Figure 30: VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat
Table 20: AC characteristics (33 MHz
bus; amended data in
Table 28: Ordering information
scheme.
data,
Figure 4: Bus master and memory devices on
Table 28: Ordering information
(t
RLRH
RHSL
Section 4.3: A fast way to modify
description modified. JEDEC signature
Changes
, t
and
Table 19
modified). Document status
RHSL
Section 6.10: Page Program (PP)
and t
Table 28: Ordering
updated.
and
scheme. Added
SHRH
Table
and added a footnote;
operation). Document
Section 4.6: Active
modes.
removed from
Section 4.2: An
and inserted in
20; amended title
scheme.
Table 19:
M25PE40
data,