M25P20-VMN6TPB NUMONYX, M25P20-VMN6TPB Datasheet - Page 9

• Manufacturer Part Number: M25P20-VMN6TPB
• Description: IC FLASH 2MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P20-VMN6TPB

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SO N
• Cell Type: NOR
• Density: 2 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 4
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P20-VMN6TPBTR

3
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time
(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all
inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become
High at the same time, and so, that the t
SPI Interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
SPI Bus Master
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Stand-by mode and not transferring data:
Bus Master and memory devices on the SPI Bus
CS2
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CS1
SDO
SDI
SCK
R
(2)
R
(2)
SHCH
C Q D
S
SPI Memory
requirement is met).
Device
W
V
CC
HOLD
R
V
(2)
SS
C Q D
S
SPI Memory
Device
Figure
W
V
HOLD
CC
R
4, is the clock polarity when the
V
(2)
SS
C Q D
S
SPI Memory
Device
W
V
CC
HOLD
AI12836
V
SS
V
V
CC
SS
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