M25P05-AVMP6G NUMONYX, M25P05-AVMP6G Datasheet - Page 31
![IC FLASH 512KBIT 50MHZ 8VFQFPN](/photos/18/97/189768/3778330_sml.jpg)
M25P05-AVMP6G
Manufacturer Part Number
M25P05-AVMP6G
Description
IC FLASH 512KBIT 50MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P05-AVMN6P.pdf
(52 pages)
Specifications of M25P05-AVMP6G
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
512K (64K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Memory Configuration
64K X 8
Ic Interface Type
Serial, SPI
Clock Frequency
50MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
VDFPN
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P05-AVMP6G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
M25P05-AVMP6G
Manufacturer:
MICRON
Quantity:
20 000
M25P05-A
6.10
Bulk erase (BE)
The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write
enable (WREN) instruction must previously have been executed. After the write enable
(WREN) instruction has been decoded, the device sets the write enable latch (WEL).
The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed bulk erase cycle (whose duration is t
bulk erase cycle is in progress, the status register may be read to check the value of the
write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk
erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the write enable latch (WEL) bit is reset.
The bulk erase (BE) instruction is executed only if both block protect (BP1, BP0) bits are 0.
The bulk erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 16. Bulk erase (BE) instruction sequence
S
C
D
0
Figure 16.
1
2
Instruction
3
4
5
6
7
AI03752D
BE
) is initiated. While the
Instructions
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