M24C08-FMB5TG STMicroelectronics, M24C08-FMB5TG Datasheet - Page 12
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M24C08-FMB5TG
Manufacturer Part Number
M24C08-FMB5TG
Description
IC EEPROM 8KBIT 400KHZ 8MLP
Manufacturer
STMicroelectronics
Datasheet
1.M24C01-WMN6TP.pdf
(39 pages)
Specifications of M24C08-FMB5TG
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
8K (1K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.7 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Package / Case
8-MLP, 8-UFDFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M24C08-FMB5TG
Manufacturer:
TI
Quantity:
24 440
Device operation
3.5
12/39
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
The device select code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the
device select code is received, the device only responds if the Chip Enable Address is the
same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with
larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0
is not available for use on devices that need to use address line A8; E1 is not available for
devices that need to use address line A9, and E2 is not available for devices that need to
use address line A10 (see
up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can
be connected to one I²C bus. In each case, and in the hybrid cases, this gives a total
memory capacity of 16 Kbits, 2 KBytes (except where M24C01 devices are used).
The 8
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 4.
1. X =
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
Table 3
th
V
IH
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
or V
Mode
(on Serial Data (SDA), most significant bit first).
IL
Operating modes
.
RW bit
Figure 2
1
0
1
1
0
0
Doc ID 5067 Rev 16
and
WC
V
V
X
X
X
X
IL
IL
(1)
Table 3
M24C16, M24C08, M24C04, M24C02, M24C01
Bytes
for details). Using the E0, E1 and E2 inputs,
16
1
1
1
1
th
bit time. If the device does not match
Start, Device Select, RW = 0
Start, Device Select, RW = 1
Start, Device Select, RW = 0, Address
reStart, Device Select, RW = 1
Similar to Current or Random Address
Read
Start, Device Select, RW = 0
Initial sequence