MT46H32M32LFCG-5 IT:A Micron Technology Inc, MT46H32M32LFCG-5 IT:A Datasheet - Page 4

• Manufacturer Part Number: MT46H32M32LFCG-5 IT:A
• Description: IC DDR SDRAM 1GBIT 152VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M32LFCG-5 IT:A

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 1G (32M x 32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 152-VFBGA
• Organization: 32Mx32
• Density: 1Gb
• Address Bus: 13b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
Figure 2:
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
BA0, BA1
Address,
CAS#
RAS#
WE#
CKE
CK#
CS#
CK
Address
register
Extended mode
Functional Block Diagram
Standard mode
register
register
Control
logic
Micron 152-ball packaged Mobile Low-Power DDR SDRAM (LPDDR) devices contain
either 1Gb LPDDR or 512Mb LPDDR die.
The 1Gb LPDDR die is a high-speed CMOS, dynamic random-access memory
containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of
the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits.
The 512Mb LPDDR die is a high-speed CMOS, dynamic random-access memory
containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each of
the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits.
Refresh
counter
address
Row-
MUX
2
2
Column-
counter/
address
control
Bank
latch
logic
decoder
address
Bank 0
row-
latch
and
1
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Sense amplifiers
DM mask logic
I/O gating
decoder
Column
memory
Bank 0
array
Bank 1
4
Bank 2
Bank 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64
64
64
Read
latch
out
CK
CK
drivers
Write
FIFO
and
32
32
CK
in
MUX
COL 0
Mask
Data
COL 0
64
8
CK
4
4
32
32
generator
DQS
registers
32
General Description
Input
©2008 Micron Technology, Inc. All rights reserved.
Data
4
4
32
32
4
4
32
DQS
DRVRS
4
RCVRS
DQ0–
DQ31
DQS0,
DQS1,
DQS2,
DQS3
DM0,
DM1,
DM2,
DM3