MT48H16M32LFCM-75 IT:B TR Micron Technology Inc, MT48H16M32LFCM-75 IT:B TR Datasheet - Page 64

• Manufacturer Part Number: MT48H16M32LFCM-75 IT:B TR
• Description: IC SDRAM 512MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H16M32LFCM-75 IT:B TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1387-2

PRECHARGE Operation
Auto Precharge
PDF: 09005aef82ea3742
512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN
The PRECHARGE command (see Figure 11 (page 31)) is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will be available for a sub-
sequent row access some specified time (
issued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select
the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are
treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands being issued to that bank.
Auto precharge is a feature that performs the same individual-bank PRECHARGE func-
tion described previously, without requiring an explicit command. This is accomplish-
ed by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE com-
mand is automatically performed upon completion of the READ or WRITE burst, except
in the continuous page burst mode where auto precharge does not apply. In the specific
case of write burst mode set to single location access with burst length set to continu-
ous, the burst length setting is the overriding setting and auto precharge does not apply.
Auto precharge is nonpersistent in that it is either enabled or disabled for each individu-
al READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. Another command cannot be issued to the same bank until the precharge time
(
sued at the earliest possible time, as described for each burst type in the Burst Type
(page 41) section.
This device supports
a single WRITE with auto precharge, issued at
be delayed until
Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre-
charge for READs and WRITEs are defined below.
READ with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a READ on bank n following the programmed CAS la-
tency. The precharge to bank n begins when the READ to bank m is registered (see
Figure 35 (page 65)).
READ with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The pre-
charge to bank n begins when the WRITE to bank m is registered (see Figure 36
(page 66)).
WRITE with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after
gins when the READ to bank m is registered. The last valid WRITE to bank n will be data-
in registered one clock prior to the READ to bank m (see Figure 41 (page 71)).
t
RP) is completed. This is determined as if an explicit PRECHARGE command was is-
t
RAS (MIN) has been satisfied.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
t
RAS lock-out. In the case of a single READ with auto precharge, or
64
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP) after the PRECHARGE command is
t
RCD (MIN), the internal precharge will
PRECHARGE Operation
t
WR is met, where
© 2007 Micron Technology, Inc. All rights reserved.
t
WR be-