MT46H16M32LFCX-6 IT:B Micron Technology Inc, MT46H16M32LFCX-6 IT:B Datasheet - Page 55
![IC DDR SDRAM 512MBIT 90VFBGA](/photos/31/34/313421/mfg557-90-vfbga_sml.jpg)
MT46H16M32LFCX-6 IT:B
Manufacturer Part Number
MT46H16M32LFCX-6 IT:B
Description
IC DDR SDRAM 512MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H16M32LFCX-5B.pdf
(98 pages)
Specifications of MT46H16M32LFCX-6 IT:B
Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
512M (16M x 32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Extended Mode Register
Figure 20: Extended Mode Register
Temperature-Compensated Self Refresh
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
En + 2
0
0
1
1
En + 1
0
1
0
1
En
0
–
...
0
–
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
Notes:
E10
0
–
E9
The EMR controls additional functions beyond those set by the mode registers. These
additional functions include drive strength, TCSR, and PASR.
The EMR is programmed via the LOAD MODE REGISTER command with BA0 = 0 and
BA1 = 1. Information in the EMR will be retained until it is programmed again, the de-
vice goes into deep power-down mode, or the device loses power.
0
This device includes a temperature sensor that is implemented for automatic control of
the self refresh oscillator. Programming the temperature-compensated self refresh
(TCSR) bits will have no effect on the device. The self refresh oscillator will continue to
refresh at the optimal factory-programmed rate for the device temperature.
–
n + 2
1
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
2. The integer n is equal to the most significant address bit.
BA1
E8
0
–
n + 1
0
BA0
E7–E0
Valid
–
An
n
...
Operation
Normal AR operation
All other states reserved
...
10
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E7
9
0
0
0
0
1
1
1
1
E6
8
0
0
1
1
0
0
1
1
55
E5
7
0
1
0
1
0
1
0
1
DS
512Mb: x16, x32 Mobile LPDDR SDRAM
6
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
E2
0
0
0
0
1
1
1
1
TCSR
4
E1
0
0
1
1
0
0
1
1
1
3
E0
0
1
0
1
0
1
0
1
2
Partial-Array Self Refresh Coverage
Full array
1/2 array
1/4 array
Reserved
Reserved
1/8 array
1/16 array
Reserved
PASR
Extended Mode Register
1
0
© 2004 Micron Technology, Inc. All rights reserved.
Address bus
Extended mode
register (Ex)