MT48LC4M32LFF5-8:G TR Micron Technology Inc, MT48LC4M32LFF5-8:G TR Datasheet - Page 44
![IC SDRAM 128MBIT 125MHZ 90VFBGA](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48LC4M32LFF5-8:G TR
Manufacturer Part Number
MT48LC4M32LFF5-8:G TR
Description
IC SDRAM 128MBIT 125MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Specifications of MT48LC4M32LFF5-8:G TR
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (4Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 9:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
CKE
H
H
L
L
n - 1
CKE
H
H
Truth Table – CKE
Notes 1–4 apply to entire table
L
L
n
Notes:
Reading or writing
Current State
Clock suspend
Clock suspend
All banks idle
All banks idle
Power-down
Power-down
Self refresh
Self refresh
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
clock edge.
MAND
clock edge n + 1 (provided that
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the
period.
the next command at clock edge n + 1.
n
is the logic state of CKE at clock edge n; CKE
n
.
t
n
XSR period. A minimum of two NOP commands must be provided during
is the command registered at clock edge n, and ACTION
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
See Table 10 on page 45
AUTO REFRESH
WRITE or NOP
Comand
44
X
X
X
X
t
CKS is met).
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile SDRAM
n - 1
Maintain clock suspend
Maintain power-down
Maintain self refresh
was the state of CKE at the previous
Clock suspend entry
Power-down entry
Exit clock suspend
Exit power-down
self refresh entry
Exit self refresh
Action
©2001 Micron Technology, Inc. All rights reserved.
n
is a result of COM-
READs
Notes
t
XSR is
t
5
6
7
XSR