IS42S16800D-7BI-TR ISSI, Integrated Silicon Solution Inc, IS42S16800D-7BI-TR Datasheet - Page 45
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS42S16800D-7BI-TR
Manufacturer Part Number
IS42S16800D-7BI-TR
Description
IC SDRAM 128MBIT 143MHZ 54BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S16800D-7TL.pdf
(62 pages)
Specifications of IS42S16800D-7BI-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (8Mx16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-BGA
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
IS42S81600D,
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
INTERNAL
COMMAND
ADDRESS
CLOCK
COMMAND
INTERNAL
CKE
ADDRESS
CLK
DQ
CLOCK
CKE
CLK
IS42S16800D
DQ
READ
BANK a,
COL n
T0
NOP
T0
NOP
T1
WRITE
BANK a,
COL n
D
T1
IN
n
NOP
T2
D
OUT
T2
n
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH; the
internal clock and related operation will resume on the
subsequent positive clock edge.
T3
D
T3
OUT
n+1
NOP
T4
D
NOP
IN
T4
n+1
NOP
D
T5
OUT
D
DON'T CARE
n+2
NOP
IN
T5
n+2
DON'T CARE
NOP
D
T6
OUT
n+3
45