MT48V8M16LFB4-8:G TR Micron Technology Inc, MT48V8M16LFB4-8:G TR Datasheet - Page 45
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MT48V8M16LFB4-8:G TR
Manufacturer Part Number
MT48V8M16LFB4-8:G TR
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC8M16LFB4-75MG_TR.pdf
(80 pages)
Specifications of MT48V8M16LFB4-8:G TR
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 10:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
Write (auto
Row active
Read (auto
precharge
precharge
disabled)
disabled)
Current
State
Any
Idle
Truth Table – Current State Bank n, Command to Bank n
Notes 1–6 apply to entire table; notes appear below table
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes:
RAS# CAS# WE# Command (Action)
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table is bank-specific, except where noted; that is, the current state is for a specific
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
after
bank and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
MAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 10 and according to Table 11 on
page 47.
X
H
H
H
H
H
H
H
H
precharge enabled:
precharge enabled:
L
L
L
L
L
L
L
L
Row active: A row in the bank has been activated, and
Row activating: Starts with registration of an ACTIVE command and ends when
t
XSR has been met (if the previous state was self refresh).
Write: A WRITE burst has been initiated, with auto precharge disabled, and has
Write w/auto
Read: A READ burst has been initiated, with auto precharge disabled, and has not
Precharging: Starts with registration of a PRECHARGE command and ends when
Read w/auto
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
Idle: The bank has been precharged, and
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
bursts/accesses and no register accesses are in progress.
yet terminated or been terminated.
not yet terminated or been terminated.
t
is met. After
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
RP is met. After
n - 1
45
was HIGH and CKE
t
RCD is met, the bank will be in the row active state.
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RP is met, the bank will be in the idle state.
t
t
128Mb: x16, x32 Mobile SDRAM
RP has been met. AFter
RP has been met. After
n
t
is HIGH (see Table 9 on page 44) and
RP has been met.
t
RCD has been met. No data
©2001 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank
RP is met, the bank
READs
Notes
11
10
10
10
10
10
10
7
7
8
8
9
8
9
t
RCD