MAX17058EVKIT# Maxim Integrated, MAX17058EVKIT# Datasheet - Page 13

• Manufacturer Part Number: MAX17058EVKIT#
• Description: Power Management IC Development Tools MAX17058 Eval Kit
• Manufacturer: Maxim Integrated
• Series: MAX17058, MAX17059r

Specifications of MAX17058EVKIT#

• Part # Aliases: 90-BCA1K#D00

The I
device in a single or multislave, and single or multimaster
system. Slave devices can share the bus by uniquely
setting the 7-bit slave address. The I
sists of a serial-data line (SDA) and serialclock line
(SCL). SDA and SCL provide bidirectional communica-
tion between the ICs slave device and a master device
at speeds up to 400kHz. The ICs’ SDA pin operates
bidirectionally; that is, when the ICs receive data, SDA
operates as an input, and when the ICs return data, SDA
operates as an open-drain output, with the host system
providing a resistive pullup. The ICs always operate as
a slave device, receiving and transmitting data under
the control of a master device. The master initiates all
transactions on the bus and generates the SCL signal, as
well as the START and STOP bits, which begin and end
each transaction.
One data bit is transferred during each SCL clock cycle,
with the cycle defined by SCL transitioning low-to-high
and then high-to-low. The SDA logic level must remain
stable during the high period of the SCL clock pulse.
Any change in SDA when SCL is high is interpreted as a
START or STOP control signal.
The bus is defined to be idle, or not busy, when no
master device has control. Both SDA and SCL remain
high when the bus is idle. The STOP condition is the
proper method to return the bus to the idle state.
The master initiates transactions with a START condition
(S) by forcing a high-to-low transition on SDA while SCL
is high. The master terminates a transaction with a STOP
condition (P), a low-to-high transition on SDA while SCL
is high. A Repeated START condition (Sr) can be used
in place of a STOP then START sequence to terminate
one transaction and begin another without returning the
bus to the idle state. In multimaster systems, a Repeated
START allows the master to retain control of the bus. The
START and STOP conditions are the only bus activities in
which the SDA transitions when SCL is high.
2
C bus system supports operation as a slave-only
START and STOP Conditions
I
2
C Bus System
2
C interface con-
Bit Transfer
1-Cell /2-Cell Li+ ModelGauge ICs
Bus Idle
Each byte of a data transfer is acknowledged with
an acknowledge bit (A) or a no-acknowledge bit (N).
Both the master and the MAX17058/MAX17059 slave
generate acknowledge bits. To generate an acknowl-
edge, the receiving device must pull SDA low before the
rising edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low until SCL returns low. To gener-
ate a no-acknowledge (also called NAK), the receiver
releases SDA before the rising edge of the acknowledge-
related clock pulse and leaves SDA high until SCL
returns low. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer can occur if a receiving device is busy or
if a system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication.
A byte of data consists of 8 bits ordered most significant
bit (MSb) first. The least significant bit (LSb) of each
byte is followed by the acknowledge bit. The IC registers
composed of multibyte values are ordered MSb first.
The MSb of multibyte registers is stored on even data-
memory addresses.
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address (SAddr) and the read/write (R/W) bit.
When the bus is idle, the ICs continuously monitor for
a START condition followed by its slave address. When
the ICs receive a slave address that matches the value
in the slave address register, they respond with an
acknowledge bit during the clock period following
the R/W bit. The 7-bit slave address is fixed to 6Ch
(write)/6Dh (read):
The R/W bit following the slave address determines
the data direction of subsequent bytes in the transfer.
R/W = 0 selects a write transaction with the following
bytes being written by the master to the slave. R/W = 1
selects a read transaction with the following bytes being
read from the slave by the master
MAX17058 /MAX17059
MAX17058 /MAX17059
SLAVE ADDRESS
Acknowledge Bits
(Table
0110110
Read/Write Bit
Slave Address
3).
Data Order
13