IS42S32400B-7TI-TR ISSI, Integrated Silicon Solution Inc, IS42S32400B-7TI-TR Datasheet - Page 28
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IS42S32400B-7TI-TR
Manufacturer Part Number
IS42S32400B-7TI-TR
Description
IC SDRAM 128MBIT 143MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32400B-7T-TR.pdf
(60 pages)
Specifications of IS42S32400B-7TI-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
86-TSOPII
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
IS42S32400B
possible CAS latency; data element n + 3 is either the last of
a burst of four or the last desired of a longer burst. Following
the PRECHARGE command, a subsequent command to the
same bank cannot be issued until t
is met. Note that part
RP
of the row precharge time is hidden during the access of the
last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same opera-
tion that would result from the same fixed-length burst with
auto precharge. The disadvantage of the PRECHARGE
command is that it requires that the command and address
buses be available at the appropriate time to issue the
command; the advantage of the PRECHARGE command is
that it can be used to truncate fixed-length or full-page
bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
28
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00J
03/03/09