MT48LC32M8A2P-7E:D Micron Technology Inc, MT48LC32M8A2P-7E:D Datasheet - Page 92

• Manufacturer Part Number: MT48LC32M8A2P-7E:D
• Description: IC SDRAM 256MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC32M8A2P-7E:D

• Package / Case: 54-TSOP II
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (8M X 8)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev. B – 10/00
Rev. A – 11/99
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Although considered final, these specifications are subject to change, as further product development and data characterization some-
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
• Updated diagram to correct
• Updated single write with AP, T3 to note 4, T4 to note 3, and
• Updated alternating bank write access, aligned
• Added new page with "FB" FBGA mechanical diagram as then-page 57.
• Added new page for FBGA marking decoder as then-page 58.
• Removed all -7 speed grade references and timing information on then-pages 1,10,
• Added (0°C ≤ T
• Changed -7 to -7E and updated any previous -7 specs to -7E specs on then-pages 36-54.
• Added notation 3 to 8E reference on front page.
• Added text under AUTO REFRESH paragraph on then-page 13, "All active banks must
• Changed "either" to "any" under Power-Down paragraph, 2nd sentence, on then-
• For I
• On then-page 35:
• Removed notes 3 through 8 on then-page 55, as they apply only to the "B4" version of
• Changed from Advanced to Preliminary.
• Initial release.
www.micron.com/productsupport Customer Comment Line: 800-932-4992
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: [phone]
Micron and the Micron logo are trademarks of Micron Technology, Inc.
page 50.
page 52.
page 53.
and 32-35.
be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO RE-
FRESH command should not be issued until the minimum
PRECHARGE command as shown in the operations section."
page 23.
64Mb SDR.
All other trademarks are the property of their respective owners.
– Removed any "CAS latency = 3" or "CL = 3" reference under the parameter/con-
– Updated I
– Updated I
– I
– Note 11, changed V
– Note 18, changed to "I
– Note 32, changed to "For -8E, CL=2 and t CK=10ns; For -75, CL=3 and t CK=7.5ns;
– Removed reference to notes 3 through 8 in TSOP package dimensions.
DD
dition column, as this became defined in notes 18 and 32 on then-page 32.
amount by the amount the frequency is altered for the test condition."
For -7E, CL=2, t CK=7.5ns."
DD5
Specifications and Conditions table:
and I
DD6
DD
DD
A
≤ +70°C) range to I
specification table values from TBD to new values.
3 -8E, 75, -7E values to 55mA, 60mA, 60mA, respectively.
parameters changed from
times occur.
IL(MIN)
DD
92
t
WR/
current will increase or decrease in a proportional
to V
t
RP to be centered around the end of
IH(MIN)
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
spec table and AC tables on then-pages 32-34.
.
t
RC to
t
WR and
256Mb: x4, x8, x16 SDRAM
t
RFC.
t
RP to T7 center on then-
t
© 1999 Micron Technology, Inc. All rights reserved.
RP has been met after the
t
WR to note 2 on then-
Revision History
t
RAS on then-