ADP2442-EVALZ Analog Devices, ADP2442-EVALZ Datasheet - Page 17

• Manufacturer Part Number: ADP2442-EVALZ
• Description: Power Management IC Development Tools Eval board
• Manufacturer: Analog Devices
• Type: DC/DC Converters, Regulators & Controllersr
• Series: ADP2442r

Specifications of ADP2442-EVALZ

• Rohs: yes
• Tool Is For Evaluation Of: ADP2442
• Factory Pack Quantity: 1

Data Sheet
ADJUSTABLE FREQUENCY
The
a resistor connected between the FREQ and AGND pins.
At power-up, the FREQ pin is forced to 1.2 V and current flows
from the FREQ pin to AGND; the current value is based on the
resistor value on the FREQ pin. Next, the same current repli-
cates in the oscillator to set the switching frequency. Note that
the resistor connected to the FREQ pin should be placed as
close as possible to the FREQ pin (see the Applications
Information section for more information).
POWER GOOD
The PGOOD pin is an open-drain output that indicates the
status of the output voltage. When the voltage of the FB pin
is between 92% and 109% of the internal reference voltage,
the PGOOD output is pulled high, provided there is a pull-up
resistor connected to the pin. When the voltage of the FB pin
is not within this range, the PGOOD output is pulled low to
AGND. The PGOOD threshold is shown in Figure 54.
Likewise, the PGOOD pin is pulled low to AGND when
•
•
•
In a typical application, a pull-up resistor connected between the
PGOOD pin and an external supply is used to generate a logic
signal. This pull-up resistor should range in value from 30 kΩ
to 100 kΩ, and the external supply should be less than 5.5 V.
MODE OF OPERATION
The SYNC/MODE pin is a multifunctional pin. The fixed fre-
quency mode is enabled when SYNC/MODE is connected to
VCC or a high logic. When SYNC/MODE is connected to
AGND, pulse skip mode is enabled. The external clock can be
applied for synchronization.
Table 5. SYNC/MODE Pin Mode of Operation
SYNC/MODE Pin
Low
High
Clock Signal
UNDERVOLTAGE
116
100
90
ADP2442
The input voltage is below the internal UVLO threshold.
The EN pin is low.
A thermal shutdown event has occurred.
V
OUT
RISING
PGOOD
features a programmable oscillator frequency with
POWER
GOOD
Figure 54. PGOOD Threshold
Mode of Operation
Pulse skip mode
Forced fixed frequency mode
Forced fixed frequency mode
OVERVOLTAGE
V
POWER
GOOD
OUT
FALLING
UNDERVOLTAGE
110
100
84
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EXTERNAL SYNCHRONIZATION
The external synchronization feature allows the switching
frequency of the device to be synchronized to an external clock.
The SYNC/MODE input accepts a logic level clock input ranging
from 300 kHz to 1 MHz (minimum pulse width = 100 ns) and
has high input impedance. For best practices, it is recommended
that the set frequency (set by the resistor at the FREQ pin) be
within ±30% of the expected clock frequency to ensure stable,
reliable, and seamless operation with or without an external
SYNC/MODE clock. When the
external clock, the regulator switching frequency is changed to
the external clock frequency.
SOFT START
The
output voltage to ramp up in a controlled manner, limiting the
inrush current during startup. The
time is 2 ms.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) function prevents the IC
from turning on when the input voltage is below the specified
operating range to avoid an undesired operating mode. If the
input voltage drops below the specified range, the UVLO func-
tion shuts off the device. The rising input voltage threshold for
the UVLO function is 4.2 V with 200 mV hysteresis. The 200 mV
of hysteresis prevents the regulator from turning on and off
repeatedly when there is a slow voltage ramp on the VIN pin.
PRECISION ENABLE/SHUTDOWN
The
shutdown the device. The ±5% accuracy lends itself to using a
resistor divider from the VIN pin (or another external supply) to
program a desired UVLO threshold that is higher than the fixed
internal UVLO of 4.2 V. The hysteresis is 100 mV.
If a resistor divider is not used, apply a logic signal instead. A
logic high enables the device, and a logic low forces the part
into shutdown mode.
ADP2442
ADP2442
3
1
2
CH1
CH3 5.00V
2.00V
has an internal soft start feature that allows the
EN
V
SS
features a precision enable pin (EN) to enable or
OUT
B
B
W
W
Figure 55. Internal Soft Start
CH2 10.0V
V
V
f
LOAD = NO LOAD
SYNC/MODE = AGND
SW
IN
OUT
= 24V
= 700kHz
= 5V
ADP2442
M1.00ms
ADP2442
T
26.00%
INTERNAL SS TIME
is synchronized to an
A CH1
internal soft start
2.18ms
ADP2442
3.44V