IS42S32400B-6TL-TR ISSI, Integrated Silicon Solution Inc, IS42S32400B-6TL-TR Datasheet - Page 24
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IS42S32400B-6TL-TR
Manufacturer Part Number
IS42S32400B-6TL-TR
Description
IC SDRAM 128MBIT 166MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S32400B-7T-TR.pdf
(60 pages)
Specifications of IS42S32400B-6TL-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS42S32400B
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length deter-
mines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
BURST DEFINITION
24
Length
Burst
Page
Full
(y)
2
4
8
(location 0-y)
n = A0-A7
A 2
0
0
0
0
1
1
1
1
Starting Column
Address
A 1
A 1
0
0
1
1
0
0
1
0
0
1
1
1
A 0
A 0
A 0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
Integrated Silicon Solution, Inc. — www.issi.com —
Type = Sequential
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A7 (x32)
when the burst length is set to two; by A2-A7 (x32) when the
burst length is set to four; and by A3-A7 (x32) when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the
boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the
burst length, the burst type and the starting column address,
as shown in BURST DEFINITION table.
Order of Accesses Within a Burst
Type = Interleaved
PRELIMINARY INFORMATION Rev. 00J
1-0-3-2-5-4-7-6
0-1-2-3-4-5-6-7
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
1-800-379-4774
03/03/09