MT48LC16M16A2P-6A:D TR Micron Technology Inc, MT48LC16M16A2P-6A:D TR Datasheet - Page 54
![IC SDRAM 256MBIT 167MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC16M16A2P-6A:D TR
Manufacturer Part Number
MT48LC16M16A2P-6A:D TR
Description
IC SDRAM 256MBIT 167MHZ 54TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC16M16A2P-75D_TR.pdf
(92 pages)
Specifications of MT48LC16M16A2P-6A:D TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1223-2
MT48LC16M16A2P-6A:D TR
MT48LC16M16A2P-6A:D TR
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Figure 22: Random READ Accesses
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
Command
Command
Data from any READ burst can be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst can be followed immediately by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst can be initi-
ated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there is a possibility that the device driving the input data will go Low-Z before
the DQ go High-Z. In this case, at least a single-cycle delay should occur between the
last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 23 (page 55) and
Figure 24 (page 56). The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-
out from the READ. After the WRITE command is registered, the DQ will go to High-Z
(or remain High-Z), regardless of the state of the DQM signal, provided the DQM was
active on the clock just prior to the WRITE command that truncated the READ com-
mand. If not, the second WRITE will be an invalid WRITE. For example, if DQM was
LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6
would be invalid.
Address
Address
1. Each READ command can be issued to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
T0
READ
Bank,
READ
Bank,
Col n
Col n
CL = 2
T1
T1
READ
READ
Bank,
Bank,
Col a
Col a
CL = 3
54
T2
T2
Bank,
Bank,
READ
READ
Col x
Col x
D
OUT
T3
T3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
READ
Bank,
Col m
READ
Bank,
Col m
D
D
OUT
OUT
T4
T4
NOP
NOP
D
D
OUT
OUT
256Mb: x4, x8, x16 SDRAM
T5
T5
NOP
NOP
D
D
OUT
OUT
© 1999 Micron Technology, Inc. All rights reserved.
T6
Don’t Care
READ Operation
NOP
D
OUT
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