MAX3881EVKIT Maxim Integrated, MAX3881EVKIT Datasheet - Page 2

• Manufacturer Part Number: MAX3881EVKIT
• Description: Interface Development Tools
• Manufacturer: Maxim Integrated
• Series: MAX3881r

_________________________ Quick Start
1) Apply +3.3V to the V
2) Select between the serial-data inputs, pins 2 and 3
3) Verify that the shunt across jumper JU7 is in place.
4) Connect a 2.488Gbps nonreturn-to-zero (NRZ) data
5) Connect the parallel output to an oscilloscope or
________________ Detailed Description
The MAX3881 EV kit simplifies evaluation of the
MAX3881, 1:16 deserializer with clock recovery. The EV
kit operates from a single +3.3V supply and includes all
the external components necessary to interface with
3.3V CML inputs and PECL outputs.
The input terminals for the differential 2.488Gbps serial-
data inputs (SDI+, SDI-, SLBI+, SLBI-) are AC-coupled
to on-board SMA connectors. Limiting amplifiers with
differential output swings between 50mVp-p and
800mVp-p can be connected directly to the SMA con-
nectors.
Internal phase adjustment is available on the MAX3881
EV kit. Phase adjust resistor R1, although not required,
can be used to shift the sampling edge of the recov-
ered clock relative to the data eye. Ensure that JU7 is
removed when adjusting PHADJ.
MAX3881 Evaluation Kit
Note: Please indicate that you are using the MAX3881 when
contacting these component suppliers.
2
AVX
Coilcraft
Sprague
ground to the GND pin.
of JU6 (SDI EN), or the system loopback inputs, pins
1 and 2 of JU6 (SLBI EN), with a 2-pin jumper.
signal (50mVp-p <V
selected inputs with 50Ω cables.
other test equipment.
_______________________________________________________________________________________
SUPPLIER
Component Suppliers
803-946-0690
847-639-6400
650-526-8393
IN
PHONE
CC
<800mVp-p differential) to the
pin. Connect power-supply
Phase Adjustment
803-626-3123
847-639-1469
650-965-1644
CML Inputs
FAX
Phase-locked loop (PLL) frequency lock conditions can
be monitored at the high-impedance loss-of-lock (LOL)
test point. A TTL high (LED off) indicates PLL frequency
lock, while a TTL low (LED on) indicates a loss-of-lock
condition. Note that the LOL circuitry will not detect a
loss-of-power condition.
___________Applications Information
PECL outputs are designed to be terminated with 50Ω
to (V
termination of 50Ω to ground, a level-shift network is
incorporated on the evaluation board to allow connec-
tion of the parallel outputs of the EV kit directly to 50Ω
equipment. The level-shift network also provides a 50Ω
impedance for matching the source impedance to the
transmission line. In addition to the level-shifting net-
work, 50Ω terminations are located at the end of each
output line (underneath the SMB connectors) in order to
properly terminate unused outputs.
Because most labs are not equipped to test all 16 par-
allel outputs at once, pads are available beneath each
SMB connector to place 50Ω termination resistors. In
addition to terminating the unconnected transmission
lines (which may act as high-frequency stubs if not ter-
minated), these 50Ω termination resistors complete the
Thèvenin equivalent load of 50Ω to (V
by the PECL outputs. Note that the Thèvenin equivalent
terminations are designed for use with a +3.3V supply.
While performance may not be severely degraded by
having some improperly terminated outputs, some
measurements (such as supply current) will be affected.
The 64-pin TQFP-EP incorporates features that provide
a very low thermal-resistance path for heat removal
from the IC. The pad is electrical ground on the
MAX3881 and must be soldered to the circuit board for
proper thermal and electrical performance.
CC
- 2V). Because most oscilloscopes provide a
Connecting PECL Outputs to 50Ω
Terminating Unused Outputs
Exposed-Pad Package
Loss-of-Lock Monitor
Oscilloscopes
CC
- 2V) required