IS42S16400D-6TL-TR ISSI, Integrated Silicon Solution Inc, IS42S16400D-6TL-TR Datasheet - Page 13
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS42S16400D-6TL-TR
Manufacturer Part Number
IS42S16400D-6TL-TR
Description
IC SDRAM 64MBIT 166MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S16400D-7TL.pdf
(57 pages)
Specifications of IS42S16400D-6TL-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
6/5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS42S16400D
DC ELECTRICAL CHARACTERISTICS
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
2. Icc
3. Input signal chnage once per 30ns.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
Symbol
I
I
V
V
I
I
I
I
I
I
I
I
I
I
I
I
OL
CC1
CC5
CC6
IL
CC2P
CC2PS
CC2N
CC2NS
CC3P
CC3PS
CC3N
CC3NS
CC4
O H
OL
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between V
chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
(3)
(3)
1
and Icc
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Operating Current
Precharge Standby Current
(In Power-Down Mode)
Precharge Standby Current
(In Non Power-Down Mode)
Active Standby Current
(In Power-Down Mode)
Active Standby Current
(In Non Power-Down Mode)
Operating Current
(In Burst Mode)
Auto-Refresh Current
Self-Refresh Current
4
depend on the output load. The maximum values for Icc
(1)
(1,2)
Test Condition
0V V
the tested pin at 0V
Output is disabled, 0V V
I
I
One Bank Operation,
Burst Length=1
t
I
CKE V
CKE V
CKE V
CKE V
t
I
BL = 4; 4 banks activated
t
t
CKE 0.2V
OUT
OUT
RC
OUT
CK
OUT
RC
CLK
= t
= t
= +2 mA
= 0mA
= t
= –2 mA
t
= 0mA
RC
IN
CK
RC
CLK
(min.)
IL
IL
IH
IH
(
(
V
(
MIN
MIN
MIN
(
DD
(
(
(
MAX
MAX
MIN
MIN
(Recommended Operation Conditions unless otherwise noted.)
)
)
)
, with pins other than
)
)
)
)
OUT
CAS latency = 3
CAS latency = 3
CAS latency = 3
V
DD
t
t
t
t
t
t
t
t
1
CK
CK
CK
CK
CK
CK
CK
CK
and Icc
=
=
=
=
= 15ns
= 15ns
= 10ns
= 15ns
4
are obtained with the output open state.
Com.
Com.
Com.
Com.
Com.
Com.
Com.
Com.
Com.
Com.
Com.
Com.
Ind.
Ind.
Ind.
Ind.
Ind.
Ind.
Ind.
Ind.
Ind.
Speed
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
-7
-7
-6
-7
-7
-6
-7
-7
—
DD
and GND for each memory
Min.
2.4
–5
–5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
130
100
145
110
150
130
150
0.4
20
15
15
30
25
25
95
85
—
2
4
1
3
7
7
5
5
5
5
1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
13