ADP5586CB-EVALZ Analog Devices, ADP5586CB-EVALZ Datasheet - Page 13

• Manufacturer Part Number: ADP5586CB-EVALZ
• Description: Interface Development Tools
• Manufacturer: Analog Devices
• Type: I/O Expansionr
• Series: ADP5586r

Specifications of ADP5586CB-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP5586
• Interface Type: I2C
• Operating Supply Voltage: 1.65 V to 3.6 V
• Description/function: Evaluation board for keypad decoder and I/O expander
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 30 uA
• For Use With: ADP5586

Data Sheet
GPI INPUT
Each of the 10 input/output lines can be configured as a general-
purpose logic input line using the GPIO_INP_EN_A and
GPIO_INP_EN_B registers (Register 0x29 and Register 0x2A).
GPIO lines can be configured to allow both input and output at
the same time. Figure 15 shows a detailed representation of the
GPI scan and detect block and its associated control and status
signals.
The current input state of each GPI can be read back using the
GPI_STATUS_x registers (Register 0x15 and Register 0x16).
Each GPI can be programmed to generate an interrupt via
the GPI_INTERRUPT_EN_x registers (Register 0x1F and
Register 0x20). The interrupt status is stored in the GPI_INT_
STAT_x registers (Register 0x13 and Register 0x14). GPI interrupts
can be programmed to trigger on the positive or negative edge
by configuring the GPI_INT_LEVEL_x registers (Register 0x1B
and Register 0x1C). If any GPI interrupt is triggered, the master
GPI_INT interrupt bit (Register 0x01, Bit 1) is also triggered.
Figure 16 shows a single GPI and how it affects its correspond-
ing status and the interrupt status bits.
GPI_INTERRUPT_EN_A[3]
GPI_INTERRUPT_EN_A[7:0]
GPI_INTERRUPT_EN_B[7:0]
RESET_TRIG_TIME[3:0]
GPI_INT_LEVEL_A[3]
GPI_INT_LEVEL_A[7:0]
GPI_INT_LEVEL_B[7:0]
GPI_EVENT_EN_A[7:0]
GPI_EVENT_EN_B[7:0]
GPI_INT_STAT_A[3]
RESET_EVENT_A[7:0]
RESET_EVENT_B[7:0]
RESET_EVENT_C[7:0]
GPIO_OUT_EN_A[7:0]
GPIO_OUT_EN_B[7:0]
GPIO_INP_EN_A[7:0]
GPIO_INP_EN_B[7:0]
GPI_STATUS_A[3]
PIN_CONFIG_A[7:0]
PIN_CONFIG_B[7:0]
RST/(R5)
(R0)
(R1)
(R2)
(R3)
(R4)
(C0)
(C1)
(C2)
(C3)
(C4)
GPI_INT
GPIO 10
GPIO 11
GPI 4
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
Figure 15. GPI Scan and Detect Block
Figure 16. Single GPI Example
CONTROL
GPI SCAN
LOGIC EVENT
KEY EVENT
GPI EVENT
I
2
C BUSY
EVENT_INT
GPI_INT
GPI_INT_STAT_A[5:0]
GPI_INT_STAT_B[4:0]
GPI_STATUS_A[5:0]
GPI_STATUS_B[4:0]
CLEARED
BY READ
UPDATE
FIFO
CLEARED
BY WRITE ‘1’
OVRFLOW_INT
[FIFO1:FIFO16]
EC[4:0]
Rev. 0 | Page 13 of 44
GPIs can be programmed to generate FIFO events via the
GPI_EVENT_EN_x registers (Register 0x1D and Register 0x1E).
GPIs in this mode do not generate GPI_INT interrupts. Instead,
they generate EVENT_INT interrupts (Register 0x01, Bit 0).
Figure 17 shows several GPI lines and their effects on the FIFO
and event count, EC[4:0].
The GPI scanner is idle until it detects a level transition. It then
scans the GPI inputs and updates accordingly. After updating,
it returns immediately to idle; it does not scan/wait, like the key
scanner. As a result, the GPI scanner can detect both edges of
narrow pulses after they pass the 70 μs input debounce filter.
GPO OUTPUT
Each of the 10 input/output lines can be configured as a general-
purpose output (GPO) line using the GPIO_OUT_EN_A and
GPIO_OUT_EN_B registers (Register 0x27 and Register 0x28).
GPIO lines can be configured to allow both input and output
at the same time (see Figure 5 for a detailed diagram of the I/O
structure). GPO configuration and usage are programmed in the
GPO_DATA_OUT_x and GPO_OUT_MODE_x registers
(Register 0x23 to Register 0x26). See the Detailed Register
Descriptions section for more information.
GPI SCAN
EVENT_INT
EC[4:0]
GPI 7
GPI 4
GPI 2
GPI 4 INACTIVE
GPI 7 INACTIVE
GPI 2 INACTIVE
GPI 2 ACTIVE
GPI 7 ACTIVE
GPI 4 ACTIVE
1
1
1
0
0
0
FIFO
1
38
43
40
40
43
38
Figure 17. Multiple GPI Example
2
3
4
5
ADP5586
6