ADP5585CP-EVALZ Analog Devices, ADP5585CP-EVALZ Datasheet - Page 15

• Manufacturer Part Number: ADP5585CP-EVALZ
• Description: Interface Development Tools LFCSP Evaluation Board
• Manufacturer: Analog Devices
• Series: ADP5585r

Specifications of ADP5585CP-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP5585
• Interface Type: I2C
• Operating Supply Voltage: 1.8 V to 3 V
• Factory Pack Quantity: 1

Data Sheet
REGISTER INTERFACE
Register access to the ADP5585 is acquired via its I
serial interface. The interface can support clock frequencies of
up to 1 MHz. If the user is accessing the FIFO or key event
counter (KEC), FIFO/KEC updates are paused. If the clock
frequency is very low, events may not be recorded in a timely
manner. FIFO or KEC updates can happen up to 23 μs after an
interrupt is asserted because of the number of I
to perform an I
an issue to the user.
Figure 23 shows a typical write sequence for programming an
internal register. The cycle begins with a start condition, followed
by the hard coded 7-bit device address, which for the ADP5585
is 0x34, followed by the R/ W bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data
line low. The address of the register to which data is to be written
is sent next. The ADP5585 acknowledges the register pointer
byte by pulling the data line low. The data byte to be written is
sent next. The ADP5585 acknowledges the data byte by pulling
the data line low. A stop condition completes the sequence.
Figure 24 shows a typical multibyte write sequence for program-
ming internal registers. The cycle begins with a start condition
followed by the 7-bit device address (0x34 for all models except
the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/ W bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data
START
START
7-BIT DEVICE ADDRESS
7-BIT DEVICE ADDRESS
2
C read or write. This delay should not present
START
0 = WRITE
7-BIT DEVICE ADDRESS
ADP5585 ACK
0
0 = WRITE
ADP5585 ACK
0
0
8-BIT REGISTER POINTER
0
8-BIT REGISTER POINTER
2
C cycles required
0 = WRITE
ADP5585 ACK
2
C-compatible
0
Figure 23. I
Figure 25. I
Figure 24. I
0
ADP5585 ACK
8-BIT REGISTER POINTER
ADP5585 ACK
Rev. C | Page 15 of 40
0
2
2
REPEAT START
2
C Single Byte Write Sequence
C Single Byte Read Sequence
C Multibyte Write Sequence
WRITE BYTE 1
0
7-BIT DEVICE ADDRESS
ADP5585 ACK
line low. The address of the register to which data is to be written
is sent next. The ADP5585 acknowledges the register pointer
byte by pulling the data line low. The data byte to be written is
sent next. The ADP5585 acknowledges the data byte by pulling
the data line low. The pointer address is then incremented to
write the next data byte, until it finishes writing the n data byte.
The ADP5585 pulls the data line low after every byte, and a stop
condition completes the sequence.
Figure 25 shows a typical byte read sequence for reading inter-
nal registers. The cycle begins with a start condition followed
by the 7-bit device address (0x34 for all models except the
ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/ W bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data line
low. The address of the register from which data is to be read is
sent next. The ADP5585 acknowledges the register pointer byte
by pulling the data line low. A start condition is repeated,
followed by the 7-bit device address (0x34 for all models except
the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/ W bit set to 1 for a read cycle. The
ADP5585 acknowledges the address byte by pulling the data
line low. The 8-bit data is then read. The host pulls the data line
high (no acknowledge), and a stop condition completes the
sequence.
ADP5585 ACK
0
0
WRITE BYTE 2
8-BIT WRITE DATA
1 = READ
ADP5585 ACK
ADP5585 ACK
1
0
0
8-BIT READ DATA
ADP5585 ACK
ADP5585 ACK
0
0
STOP
WRITE BYTE n
NO ACK
ADP5585 ACK
1
STOP
ADP5585
0
STOP