MA240026 Microchip Technology, MA240026 Datasheet - Page 212
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MA240026
Manufacturer Part Number
MA240026
Description
Daughter Cards & OEM Boards PIC24FJ16MC102 Plug-In Module
Manufacturer
Microchip Technology
Datasheet
1.MA240026.pdf
(304 pages)
Specifications of MA240026
Rohs
yes
Data Bus Width
16 bit
Description/function
PIC24F 28 Pin QFN to 100 Pin Plug-in-Module
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MA240026
Manufacturer:
MICROCHIP
Quantity:
12 000
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- Download datasheet (3Mb)
PIC24FJ16MC101/102
REGISTER 22-2:
DS39997B-page 212
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-10
bit 9
bit 8
bit 7
bit 6
bit 5-2
bit 1-0
EDG1MOD
EDG2MOD
R/W-0
R/W-0
EDG1MOD: Edge 1 Edge Sampling Selection bit
1 = Edge 1 is edge sensitive
0 = Edge 1 is level sensitive
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 programmed for a positive edge response
0 = Edge 1 programmed for a negative edge response
EDG1SEL<3:0>: Edge 1 Source Select bits
1xxx = Reserved
01xx = Reserved
0011 = CTED1 pin
0010 = CTED2 pin
0001 = OC1 module
0000 = Timer1 module
EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control the edge source.
1 = Edge 2 has occurred
0 = Edge 2 has not occurred
EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control the edge source.
1 = Edge 1 has occurred
0 = Edge 1 has not occurred
EDG2MOD: Edge 2 Edge Sampling Selection bit
1 = Edge 2 is edge sensitive
0 = Edge 2 is level sensitive
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 programmed for a positive edge response
0 = Edge 2 programmed for a negative edge response
EDG2SEL<3:0>: Edge 2 Source Select bits
1xxx = Reserved
01xx = Reserved
0011 = CTED2 pin
0010 = CTED1 pin
0001 = Comparator 2 module
0000 = IC1 module
Unimplemented: Read as ‘0’
EDG1POL
EDG2POL
R/W-0
R/W-0
CTMUCON2: CTMU CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
EDG2SEL<3:0>
Preliminary
EDG1SEL<3:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
© 2011 Microchip Technology Inc.
x = Bit is unknown
EDG2STAT
R/W-0
U-0
—
EDG1STAT
R/W-0
U-0
—
bit 8
bit 0
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