DS4830EVKIT# Maxim Integrated, DS4830EVKIT# Datasheet - Page 8

• Manufacturer Part Number: DS4830EVKIT#
• Description: Development Boards & Kits - Other Processors DS4830 Eval Kit
• Manufacturer: Maxim Integrated

Specifications of DS4830EVKIT#

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: DS4830
• Interface Type: I2C
• Operating Supply Voltage: 3 V to 3.6 V
• Part # Aliases: 90-4830T#EVK

SPI DIGITAL INTERFACE SPECIFICATION (continued)
(V
ELECTRICAL CHARACTERISTICS: JTAG INTERFACE
(V
Note 1: All voltages are referenced to GND. Currents entering the IC are specified as positive, and currents exiting the IC are
Note 2: Maximum current assuming 100% CPU duty cycle.
Note 3: This value does not include current in GPIO, SCL, SDA, MDIO, MDI, MCL, REFINA, and REFINB.
Note 4: Depends on voltage on REFINA/B using internal reference.
Note 5: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock.
Note 6: Guaranteed by design.
Note 7: ADC conversions are delayed up to 1.6Fs if the fast comparator is sampling the selected ADC channel. This can cause a
Note 8: Temperature readings average 64 times.
Note 9: Programming time does not include overhead associated with the utility ROM interface.
Note 10: f
Note 11: The maximum t
Note 12: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V
Note 13: C
Note 14: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Maxim Integrated
SSPICS Inactive
SSPICK Inactive to SSPICS
Rising
SSPIDO Output Disabled After
SSPICS Edge Rise
JTAG Logic Reference
TCK High Time
TCK Low Time
TCK Low to TDO Output
TMS, TDI Input Setup to TCK High
TMS, TDI Input Hold After TCK
High
DD
DD
= 3.0V to 3.6V, T
= 3.0V to 3.6V, T
specified as negative.
slight decrease in the ADC sampling rate.
bridge the undefined region of the falling edge of SCL.
SCL
PARAMETER
B
PARAMETER
—Total capacitance of one bus line in pF.
must meet the minimum clock low time plus the rise/fall times.
A
A
= -40NC to +85NC, unless otherwise noted.) (See
= -40NC to +85NC, unless otherwise noted.)
HD:DAT
need only be met if the device does not stretch the low period (t
SYMBOL
SYMBOL
t
t
t
t
SSH
t
V
SLH
DVTH
THDX
t
SD
t
TLQ
t
REF
TH
TL
CONDITIONS
CONDITIONS
(Figure
Optical Microcontroller
Figure 3
5)
and
Figure
t
SSPICK
t
t
SPI_RF
SPI_RF
4.)
MIN
0.25
0.25
MIN
0.5
0.5
LOW
+
) of the SCL signal.
V
IH:MIN
TYP
TYP
DD
/2
of the SCL signal) to
DS4830
2t
2t
0.125
MAX
SSPICK
MAX
SPI_RF
+
UNITS
UNITS
ns
ns
ns
Fs
Fs
Fs
Fs
Fs
V
8