TWR-P1025-KIT Freescale Semiconductor, TWR-P1025-KIT Datasheet - Page 14

• Manufacturer Part Number: TWR-P1025-KIT
• Description: Development Boards & Kits - Other Processors QORIQ P1 TWR KIT
• Manufacturer: Freescale Semiconductor

Specifications of TWR-P1025-KIT

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: P1025
• Core: e500mc
• Interface Type: SPI, UART, USB
• Data Bus Width: 16 bit
• For Use With: P1025

Hardware Description
clock also feeds the PLLs in the e500 core and the PLL that create clocks for the integrated flash controller.
Note that the divide-by-two CCB clock divider and the divide-by-n CCB clock divider, shown in
Figure
3-2, are located in the DDR and IFC blocks, respectively.
A SYSCLK of 66.667 MHz will be the default used for the design.
The DDR memory controller complex may use the platform clock or the DDRCLK, which is multiplied
up using a separate PLL to create a unique DDR memory controller complex clock. In this case, the DDR
complex operates asynchronous with respect to the platform clock and runs at a fixed data rate of
667MTps.
The clocks for the PCI Express and SGMII interfaces are derived from a PLL in the SerDes block. This
PLL is driven by a reference clock (SD_REF_CLK/SD_REF_CLK) whose input frequency is a function
of the bit rate being used (100 MHz or 125 MHz). Note that for proper PCI Express operation, the CCB
clock frequency must be greater than 62.5 MHz.
The Ethernet blocks operate asynchronously with respect to the rest of the device. These blocks use receive
and transmit clocks supplied by their respective PHY chips, plus a 125-MHz clock input for gigabit
protocols. Data transfers are synchronized to the CCB clock internally.
Figure 3-2. P1025 Clocking Scheme
Table 3-1
and
Table 3-2
describe the CCB and core platform frequency ratio selection.
Table 3-3
describes
the DDRCLK input ratio to DDR controller clock ratio.
The DDR runs at a fixed x10 multiplier to DDR_CLK.
TWR-P1025 Hardware User Guide, Rev. 2
Freescale Semiconductor
3