MAX9760EVKIT Maxim Integrated, MAX9760EVKIT Datasheet - Page 14

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MAX9760EVKIT

Manufacturer Part Number
MAX9760EVKIT
Description
Amplifier IC Development Tools
Manufacturer
Maxim Integrated
Series
MAX9760, MAX9761, MAX9762, MAX9763r
Datasheet
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
MAX9760/MAX9761 Evaluation
System/Evaluation Kit
Figure 13. MAX9760 EV Kit Schematic (Modified for MAX9763)
DGND
J6-10
J6-12
J6-14
J6-16
J6-18
J6-19
J6-2
J6-4
J6-5
J6-6
J6-8
HEADER 20 PIN
GAINA/B
SDA
HPS
SCL
DGND
J6
10kΩ
J6-11
J6-13
J6-15
J6-17
J6-20
J6-3
J6-7
J6-9
J6-1
R16
DGND
2
1
VDD
3
VDD
JU5
10kΩ
R15
HEADER 12 PIN
DGND
SHDN
JU1-1
JU1-4
JU1-5
JU1-8
JU1-9
JU1-12
1
2
VDD
3
JU4
JU1
1kΩ
SDA
SCL
INT
JU1-10
JU1-11
R14
J1
J2
J3
J4
JU1-2
JU1-3
JU1-6
JU1-7
DGND
1
2
VDD
3
JU3
2
1
2
1
2
1
2
1
SGND
SGND
SGND
SGND
1kΩ
R13
DGND
2
220µF
1
VDD
3
SDA
INT
6.3V
C11
0.68µF
0.68µF
0.68µF
0.68µF
JU2
20V
20V
20V
20V
C1
C2
C3
C4
220µF
Printed USA
DGND
6.3V
C14
RPGND
SCL
15kΩ
15kΩ
15kΩ
15kΩ
C12
1µF
1%
1%
1%
1%
R1
R2
R3
R4
SGND
220µF
6.3V
C15
28
14
19
20
15
17
1
2
5
6
4
LPGND
IN1/2
GAINA/B
MUTE
HPS_EN
SHDN
INL1
INR1
INL2
INR2
SV
BIAS
DD
LPGND
GND PGND
PV
13
DD
11
MAX9763
PV
9
VDD
U1
DD
RPGND
PGND
25
23
V
DD
PGND
GAINRA
GAINRB
GAINLA
GAINLB
3
GAINM
OUTR+
OUTR-
OUTL+
27
HPS
N.C.
C13
1µF
SGND
18
21
22
24
26
16
7
8
10
12
is a registered trademark of Maxim Integrated Products.
0.047µF
0.047µF
100pF
100pF
C8
C6
C7
C5
JU7
SGND
MONO
33.2kΩ
33.2kΩ
N.C.
3
TB2
TB1
1
2
1%
1%
R8
R7
TERMINAL BLOCK
TERMINAL BLOCK
27.4kΩ
27.4kΩ
TB2-1
TB1-1
100pF
15kΩ
15kΩ
47kΩ
15kΩ
C16
R18
R10
R19
1%
1%
1%
1%
1%
R6
R9
R5
TB2-2
TB1-2
RPGND LPGND
220µF
220µF
6.3V
6.3V
C10
C9
RPGND
LPGND
680kΩ
R12
10kΩ
R11
10kΩ
GAINA/B
DGND
R17
JU6
SHDN
SDA
HPS
SCL
INT
HPS
VDD
SGND
SGND
VDD
4
3
2
1
RIGHT
LEFT
GND
GAINA/B
HPS_EN
MUTE
SHDN
IN1/2
GND
VDD
HPS
J5

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